leds_4bit_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

	C_OPB_AWIDTH = 32
	C_INCLUDE_WR_BUF = 0
	C_INCLUDE_ADDR_CNTR = 0
	C_FAMILY = "virtex2p"
	C_DEV_MIR_ENABLE = 0
	C_DEV_BURST_ENABLE = 0
	C_DEV_BLK_ID = 0
	C_ARD_NUM_CE_ARRAY = (2)
	C_ARD_ID_ARRAY = (100)
	C_ARD_DWIDTH_ARRAY = (32)
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
	                               (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000",
	                          "0000000000000000000000000000000001000000000000000000000000001111")
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2149: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2149: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2175: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2175: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2198: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" line 2198: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
INFO:Xst:1304 - Contents of register <opb_seqaddr_s0> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <opb_seqaddr_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <bus2ip_rdreq_s1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <bus2ip_wrreq_s1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <opb_seqaddr_s0_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <bus2ip_burst_s1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <last_burstrd_xferack_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <last_burstrd_xferack_d2> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <bus2ip_burst_s1_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
Entity <opb_bam> analyzed. Unit <opb_bam> generated.

Analyzing generic Entity <pselect.1> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_BAR = "01000000000000000000000000000000"
	C_AW = 32
	C_AB = 28
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.1> analyzed. Unit <pselect.1> generated.

Analyzing generic Entity <pselect.2> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_BAR = "0000"
	C_AB = 0
	C_AW = 4
Entity <pselect.2> analyzed. Unit <pselect.2> generated.

Analyzing generic Entity <pselect.3> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_BAR = "0"
	C_AW = 1
	C_AB = 1
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.3> analyzed. Unit <pselect.3> generated.

Analyzing generic Entity <pselect.4> in library <proc_common_v2_00_a> (Architecture <imp>).
	C_AB = 1
	C_BAR = "1"
	C_AW = 1
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect.4> analyzed. Unit <pselect.4> generated.

Analyzing generic Entity <IPIF_Steer> in library <proc_common_v2_00_a> (Architecture <IMP>).
	C_DWIDTH = 32
	C_SMALLEST = 32
	C_AWIDTH = 32
Entity <IPIF_Steer> analyzed. Unit <IPIF_Steer> generated.

Analyzing generic Entity <GPIO_Core> in library <opb_gpio_v3_01_b> (Architecture <IMP>).
	C_AW = 32
	C_ALL_INPUTS_2 = false
	C_ALL_INPUTS = false
	C_DOUT_DEFAULT = "00000000000000000000000000000000"
	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
	C_DW = 32
	C_GPIO_WIDTH = 4
	C_INTERRUPT_PRESENT = false
	C_IS_BIDIR = false
	C_IS_BIDIR_2 = true
	C_IS_DUAL = false
	C_OPB_DWIDTH = 32
	C_TRI_DEFAULT = "11111111111111111111111111111111"
	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
    Set user-defined property "INIT =  0" for instance <READ_REG_GEN[0].READ_REG_FF_I> in unit <GPIO_Core>.
    Set user-defined property "INIT =  0" for instance <READ_REG_GEN[1].READ_REG_FF_I> in unit <GPIO_Core>.
    Set user-defined property "INIT =  0" for instance <READ_REG_GEN[2].READ_REG_FF_I> in unit <GPIO_Core>.
    Set user-defined property "INIT =  0" for instance <READ_REG_GEN[3].READ_REG_FF_I> in unit <GPIO_Core>.
WARNING:Xst:819 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/gpio_core.vhd" line 427: The following signals are missing in the process sensitivity list:
   dout_default_i.
WARNING:Xst:819 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/gpio_core.vhd" line 449: The following signals are missing in the process sensitivity list:
   tri_default_i.
Entity <GPIO_Core> analyzed. Unit <GPIO_Core> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <pselect_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A> is never used.
WARNING:Xst:1780 - Signal <lut_out> is never used or assigned.
Unit <pselect_2> synthesized.


Synthesizing Unit <IPIF_Steer>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd".
WARNING:Xst:647 - Input <Addr> is never used.
WARNING:Xst:647 - Input <Decode_size> is never used.
Unit <IPIF_Steer> synthesized.


Synthesizing Unit <GPIO_Core>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/gpio_core.vhd".
WARNING:Xst:647 - Input <select_Reg> is never used.
WARNING:Xst:647 - Input <ABus_Reg<0:28>> is never used.
WARNING:Xst:647 - Input <ABus_Reg<30:31>> is never used.
WARNING:Xst:647 - Input <GPIO2_IO_I> is never used.
WARNING:Xst:647 - Input <BE_Reg<0:2>> is never used.
WARNING:Xst:1305 - Output <GPIO2_IO_O> is never assigned. Tied to value 0000.
WARNING:Xst:1305 - Output <GPIO2_IO_T> is never assigned. Tied to value 0000.
WARNING:Xst:1305 - Output <GPIO2_t_out> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <GPIO2_in> is never used.
WARNING:Xst:1305 - Output <GPIO2_d_out> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <seqAddr_Reg> is never used.
WARNING:Xst:647 - Input <GPIO_IO_I> is never used.
WARNING:Xst:1780 - Signal <gpio2_data_in_xor_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <or_ints> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_Data_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_Data_In> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio_data_in_xor> is never used or assigned.
WARNING:Xst:646 - Signal <dout2_default_i> is assigned but never used.
WARNING:Xst:1780 - Signal <gpio_data_in_xor_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <or_ints2> is never used or assigned.
WARNING:Xst:646 - Signal <tri2_default_i> is assigned but never used.
WARNING:Xst:1780 - Signal <gpio2_data_in_xor> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_OE> is never used or assigned.
    Found 4x2-bit ROM for signal <$rom0000>.
    Found 4-bit register for signal <gpio_Data_In>.
    Found 4-bit register for signal <gpio_Data_Out>.
    Found 4-bit register for signal <gpio_OE>.
    Found 1-bit register for signal <gpio_xferAck_Reg>.
    Found 1-bit register for signal <iGPIO_xferAck>.
    Found 4-bit 4-to-1 multiplexer for signal <Read_Reg_In>.
    Summary:
	inferred   1 ROM(s).
	inferred  14 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <GPIO_Core> synthesized.


Synthesizing Unit <pselect_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A<28:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<7>> is never used or assigned.
Unit <pselect_1> synthesized.


Synthesizing Unit <pselect_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:1780 - Signal <lut_out<1>> is never used or assigned.
Unit <pselect_3> synthesized.


Synthesizing Unit <pselect_4>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:1780 - Signal <lut_out<1>> is never used or assigned.
Unit <pselect_4> synthesized.


Synthesizing Unit <opb_bam>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd".
WARNING:Xst:647 - Input <IP2RFIFO_WrRelease> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrRestore> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrMark> is never used.
WARNING:Xst:647 - Input <IP2WFIFO_RdMark> is never used.
WARNING:Xst:647 - Input <IP2Bus_Clk> is never used.
WARNING:Xst:647 - Input <IP2Bus_AddrAck> is never used.