plb2opb_wrapper_xst.prj

本系统由服务器软件控制平台和fpga硬件处理系统组成

VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/family.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/pselect.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_gate.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_srl16x30.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_pkg.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_plb_if.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_xfer_if.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if_fifo.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_opb_if.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_besr.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_interrupt.vhd
VHDL plb2opb_bridge_v1_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge.vhd
vhdl work ../hdl/plb2opb_wrapper.vhd