system.ucf

本系统由服务器软件控制平台和fpga硬件处理系统组成

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin IOSTANDARD = LVCMOS25;
Net sys_rst_pin LOC=AH5;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints

#### Module RS232_Uart_1 constraints

Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;

#### Module LEDs_4Bit constraints

Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=AC4;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 12;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=AC3;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 12;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=AA6;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 12;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=AA5;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 12;

#### Module DIPSWs_4Bit constraints

Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<0> LOC=AC11;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<1> LOC=AD11;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<2> LOC=AF8;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> LOC=AF9;
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;

#### Module PushButtons_5Bit constraints

Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<0> LOC=AG5;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<1> LOC=AH4;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<2> LOC=AG3;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<3> LOC=AH1;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<4> LOC=AH2;
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<4> IOSTANDARD = LVTTL;

#### Module PS2_Ports constraints


#### Module PS2_Ports_IO_ADAPTER constraints

Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin LOC=AG2;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin LOC=AG1;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin LOC=AD6;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin LOC=AD5;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin DRIVE = 8;

Net fpga_0_net_gnd_pin LOC=G12;
Net fpga_0_net_gnd_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_pin SLEW = SLOW;
Net fpga_0_net_gnd_pin DRIVE = 6;
Net fpga_0_net_gnd_1_pin LOC=D15;
Net fpga_0_net_gnd_1_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_1_pin SLEW = SLOW;
Net fpga_0_net_gnd_1_pin DRIVE = 6;
Net fpga_0_net_gnd_2_pin LOC=E15;
Net fpga_0_net_gnd_2_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_2_pin SLEW = SLOW;
Net fpga_0_net_gnd_2_pin DRIVE = 6;
Net fpga_0_net_gnd_3_pin LOC=G10;
Net fpga_0_net_gnd_3_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_3_pin SLEW = SLOW;
Net fpga_0_net_gnd_3_pin DRIVE = 6;
Net fpga_0_net_gnd_4_pin LOC=E10;
Net fpga_0_net_gnd_4_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_4_pin SLEW = SLOW;
Net fpga_0_net_gnd_4_pin DRIVE = 6;
Net fpga_0_net_gnd_5_pin LOC=G8;
Net fpga_0_net_gnd_5_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_5_pin SLEW = SLOW;
Net fpga_0_net_gnd_5_pin DRIVE = 6;
Net fpga_0_net_gnd_6_pin LOC=H9;
Net fpga_0_net_gnd_6_pin IOSTANDARD = LVTTL;
Net fpga_0_net_gnd_6_pin SLEW = SLOW;
Net fpga_0_net_gnd_6_pin DRIVE = 6;