system.par

本系统由服务器软件控制平台和fpga硬件处理系统组成

Release 8.2.02i par I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

3419FB7DB1FB470::  Mon Mar 31 08:31:02 2008

par -w -ol high system_map.ncd system.ncd system.pcf 


Constraints file: system.pcf.
Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.
   "system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts)


Device speed data version:  "PRODUCTION 1.92 2006-08-18".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 16      6%
   Number of DCMs                      1 out of 8      12%
   Number of External IOBs            72 out of 556    12%
      Number of LOCed IOBs            28 out of 72     38%

   Number of PPC405s                   1 out of 2      50%
   Number of RAMB16s                  32 out of 136    23%
   Number of SLICEs                 1442 out of 13696  10%


Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 18 secs 
Finished initial Timing Analysis.  REAL time: 18 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98e443) REAL time: 22 secs 

Phase 2.7
INFO:Place:834 - Only a subset of IOs are locked. Out of 72 IOs, 28 are locked and 44 are not locked. If you would like
   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more). 
Phase 2.7 (Checksum:1312cfe) REAL time: 22 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 22 secs 

Phase 4.2
.....


Phase 4.2 (Checksum:989a03) REAL time: 37 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 37 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 39 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 39 secs 

Phase 8.8
..................
.......
..................
.......
.......
...
Phase 8.8 (Checksum:e05947) REAL time: 1 mins 1 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 mins 1 secs 

Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 1 mins 27 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 1 mins 27 secs 

Phase 12.27
Phase 12.27 (Checksum:7270df4) REAL time: 1 mins 28 secs 

Phase 13.24
Phase 13.24 (Checksum:7bfa473) REAL time: 1 mins 28 secs 

Writing design to file system.ncd


Total REAL time to Placer completion: 1 mins 35 secs 
Total CPU time to Placer completion: 1 mins 12 secs 

Starting Router

Phase 1: 12094 unrouted;       REAL time: 2 mins 15 secs 

Phase 2: 10096 unrouted;       REAL time: 2 mins 20 secs 

Phase 3: 1757 unrouted;       REAL time: 2 mins 37 secs 

Phase 4: 1757 unrouted; (0)      REAL time: 2 mins 39 secs 

Phase 5: 1757 unrouted; (0)      REAL time: 2 mins 39 secs 

Phase 6: 1757 unrouted; (0)      REAL time: 2 mins 40 secs 

Phase 7: 0 unrouted; (0)      REAL time: 2 mins 53 secs 

Phase 8: 0 unrouted; (0)      REAL time: 3 mins 2 secs 


Total REAL time to Router completion: 3 mins 6 secs 
Total CPU time to Router completion: 2 mins 8 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|plb_bram_if_cntlr_1_ |              |      |      |            |             |
|       port_BRAM_Clk |     BUFGMUX7S| No   | 1089 |  0.272     |  1.258      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.995
   The MAXIMUM PIN DELAY IS:                               7.818
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.800

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
        6266        3553         828         177          89           0

Timing Score: 0

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP  | 10.000ns   | 9.721ns    | 4      | 0.279ns    | 0       
  "dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin     |            |            |        |            |         
       HIGH 50%                             |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A        | N/A        | N/A    | N/A        | N/A     
  pin" 10 ns HIGH 50%                       |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  PATH "TS_RST1_path" TIG                   | N/A        | 3.759ns    | 1      | N/A        | N/A     
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 mins 16 secs 
Total CPU time to PAR completion: 2 mins 15 secs 

Peak Memory Usage:  258 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file system.ncd



PAR done!