system_map.mrp

本系统由服务器软件控制平台和fpga硬件处理系统组成

Release 8.2.02i Map I.34
Xilinx Mapping Report File for Design 'system'

Design Information
------------------
Command Line   : map -o system_map.ncd -pr b system.ngd system.pcf 
Target Device  : xc2vp30
Target Package : ff896
Target Speed   : -7
Mapper Version : virtex2p -- $Revision: 1.34.32.1 $
Mapped Date    : Mon Mar 31 08:30:20 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:       1,360 out of  27,392    4%
  Number of 4 input LUTs:           1,405 out of  27,392    5%
Logic Distribution:
  Number of occupied Slices:        1,442 out of  13,696   10%
  Number of Slices containing only related logic:   1,442 out of   1,442  100%
  Number of Slices containing unrelated logic:          0 out of   1,442    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,763 out of  27,392    6%
  Number used as logic:             1,405
  Number used as a route-thru:         82
  Number used for Dual Port RAMs:     212
    (Two LUTs used per Dual Port RAM)
  Number used as Shift registers:      64

  Number of bonded IOBs:               72 out of     556   12%
    IOB Flip Flops:                    63
  Number of PPC405s:                   1 out of       2   50%
  Number of Block RAMs:                32 out of     136   23%
  Number of GCLKs:                      1 out of      16    6%
  Number of DCMs:                       1 out of       8   12%
  Number of GTs:                        0 out of       8    0%
  Number of GT10s:                      0 out of       0    0%

Total equivalent gate count for design:  2,156,128
Additional JTAG gate count for IOBs:  3,456
Peak Memory Usage:  237 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network plb_PLB_compress has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 493
   more times for the following (max. 5 shown):
   opb_M_seqAddr,
   plb_PLB_rdPrim,
   plb_PLB_pendReq,
   opb_M_busLock,
   plb_PLB_lockErr
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMISOCMCLK for the
   comp ppc405_0/ppc405_0/PPC405_i is not connected to the output of a DCM
   driven clock buffer.
WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMDSOCMCLK for the
   comp ppc405_0/ppc405_0/PPC405_i is not connected to the output of a DCM
   driven clock buffer.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "dcm_0/dcm_0/Using_BUGF_for_CLK0.CLK0_BUFG_INST" (output
   signal=plb_bram_if_cntlr_1_port_BRAM_Clk)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
 388 block(s) removed
 173 block(s) optimized away
 720 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "plb_PLB_compress" is loadless and has been removed.
 Loadless block "plb/plb/I_PLB_ADDRPATH/I_PLBCMPRS_MUX/_or00001" (ROM) removed.
  The signal "plb_M_compress<0>" is loadless and has been removed.
  The signal "plb_M_compress<1>" is loadless and has been removed.
The signal "opb_M_seqAddr" is loadless and has been removed.
 Loadless block
"plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[70].RAM_FF_I" (SFF)
removed.
  The signal "plb2opb/plb2opb/XFER_IF_I/dout<70>" is loadless and has been
removed.
The signal "plb_PLB_rdPrim" is loadless and has been removed.
 Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/PLB_rdPrim1" (ROM) removed.
  The signal "plb/plb/I_PLB_ARBITER_LOGIC/plb_rdprimreg_i" is loadless and has
been removed.
   Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/plb_rdprimreg_i" (SFF) removed.
    The signal "plb/plb/I_PLB_ARBITER_LOGIC/rdPrimIn" is loadless and has been
removed.
     Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/rdPrimIn" (ROM) removed.
      The signal "plb/N270" is loadless and has been removed.
       Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/rdPrimIn_SW0" (ROM) removed.
The signal "plb_PLB_pendReq" is loadless and has been removed.
 Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/REQ_MASTERS_MUXES[3].
I_MASTERREQ_MUX" (MUX) removed.
  The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/req_mux<2>" is
loadless and has been removed.
   Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/REQ_MASTERS_MUXES[2].
I_MASTERREQ_MUX" (MUX) removed.
    The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/req_mux<1>" is
loadless and has been removed.
     Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/I_REQ_MUX1" (MUX)
removed.
      The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/req_mux<0>" is
loadless and has been removed.
       Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/I_REQ_MUX0" (MUX)
removed.
        The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/arbSecWrInProgReg_n"
is loadless and has been removed.
         Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/arbSecWrInProgReg_n1_
INV_0" (BUF) removed.
      The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/arbSecRdInProgReg_n"
is loadless and has been removed.
       Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/arbSecRdInProgReg_n1_
INV_0" (BUF) removed.
    The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/m_request_n<0>" is
loadless and has been removed.
     Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/_not00001_INV_0"
(BUF) removed.
  The signal
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/m_request_n<1>" is
loadless and has been removed.
   Loadless block
"plb/plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_PEND_REQ/_not00011_INV_0"
(BUF) removed.
The signal "opb_M_busLock" is loadless and has been removed.
 Loadless block "plb2opb/plb2opb/OPB_IF_I/BGO_busLock1" (ROM) removed.
  The signal "plb2opb/plb2opb/opb_xfer_rd_data<69>" is loadless and has been
removed.
   Loadless block
"plb2opb/plb2opb/XFER_IF_I/DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[69].RAM_FF_I" (SFF)
removed.
    The signal "plb2opb/plb2opb/XFER_IF_I/dout<69>" is loadless and has been
removed.
  The signal "plb2opb/plb2opb/OPB_IF_I/hold_buslock" is loadless and has been
removed.
   Loadless block "plb2opb/plb2opb/OPB_IF_I/hold_buslock" (SFF) removed.
    The signal "plb2opb/plb2opb/OPB_IF_I/_and0002" is loadless and has been removed.
     Loadless block "plb2opb/plb2opb/OPB_IF_I/_and00021" (ROM) removed.
      The signal "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d3" is loadless and has
been removed.
       Loadless block "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d3" (FF) removed.
        The signal "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d2" is loadless and has
been removed.
         Loadless block "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d2" (FF) removed.
          The signal "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d1" is loadless and has
been removed.
           Loadless block "plb2opb/plb2opb/XFER_IF_I/PLB_hold_buslock_d1" (FF) removed.
            The signal "plb2opb/plb2opb/PLB_IF_I/PLB_hold_buslock" is loadless and has been
removed.
             Loadless block "plb2opb/plb2opb/PLB_IF_I/PLB_hold_buslock" (SFF) removed.
              The signal "plb2opb/plb2opb/PLB_IF_I/_and0000" is loadless and has been removed.
               Loadless block "plb2opb/plb2opb/PLB_IF_I/_and00001" (ROM) removed.
                The signal "plb_PLB_busLock" is loadless and has been removed.
                 Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/I_BUSLOCK_SM/PLB_busLock1" (ROM)
removed.
                  The signal "plb/plb/I_PLB_ARBITER_LOGIC/I_BUSLOCK_SM/plb_buslock_reg" is
loadless and has been removed.
                   Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/I_BUSLOCK_SM/plb_buslock_reg" (SFF)
removed.
                    The signal "plb/plb/I_PLB_ARBITER_LOGIC/I_BUSLOCK_SM/_or0000" is loadless and
has been removed.
                     Loadless block "plb/plb/I_PLB_ARBITER_LOGIC/I_BUSLOCK_SM/_or0000" (ROM) removed.
                      The signal "plb/PLB_Srearbitrate" is loadless and has been removed.
                       Loadless block "plb/plb/I_PLB_SLAVE_ORS/REARB_OR/_or00001" (ROM) removed.
              The signal "plb2opb/plb2opb/PLB_IF_I/_xor0027" is loadless and has been removed.
               Loadless block "plb2opb/plb2opb/PLB_IF_I/_xor00271" (ROM) removed.