📄 system.pcf

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//! **************************************************************************
// Written by: Map I.34 on Mon Mar 31 08:30:55 2008
//! **************************************************************************

SCHEMATIC START;
COMP "fpga_0_net_gnd_1_pin" LOCATE = SITE "D15" LEVEL 1;
COMP "fpga_0_net_gnd_2_pin" LOCATE = SITE "E15" LEVEL 1;
COMP "fpga_0_net_gnd_3_pin" LOCATE = SITE "G10" LEVEL 1;
COMP "fpga_0_net_gnd_4_pin" LOCATE = SITE "E10" LEVEL 1;
COMP "fpga_0_net_gnd_5_pin" LOCATE = SITE "G8" LEVEL 1;
COMP "fpga_0_net_gnd_6_pin" LOCATE = SITE "H9" LEVEL 1;
COMP "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin" LOCATE = SITE "AG2" LEVEL
        1;
COMP "fpga_0_LEDs_4Bit_GPIO_IO_pin<0>" LOCATE = SITE "AC4" LEVEL 1;
COMP "fpga_0_LEDs_4Bit_GPIO_IO_pin<1>" LOCATE = SITE "AC3" LEVEL 1;
COMP "fpga_0_LEDs_4Bit_GPIO_IO_pin<2>" LOCATE = SITE "AA6" LEVEL 1;
COMP "fpga_0_LEDs_4Bit_GPIO_IO_pin<3>" LOCATE = SITE "AA5" LEVEL 1;
COMP "fpga_0_net_gnd_pin" LOCATE = SITE "G12" LEVEL 1;
COMP "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin" LOCATE = SITE "AD5" LEVEL
        1;
COMP "sys_clk_pin" LOCATE = SITE "AJ15" LEVEL 1;
COMP "fpga_0_DIPSWs_4Bit_GPIO_IO_pin<0>" LOCATE = SITE "AC11" LEVEL 1;
COMP "fpga_0_DIPSWs_4Bit_GPIO_IO_pin<1>" LOCATE = SITE "AD11" LEVEL 1;
COMP "fpga_0_DIPSWs_4Bit_GPIO_IO_pin<2>" LOCATE = SITE "AF8" LEVEL 1;
COMP "fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3>" LOCATE = SITE "AF9" LEVEL 1;
COMP "sys_rst_pin" LOCATE = SITE "AH5" LEVEL 1;
COMP "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin" LOCATE = SITE "AD6" LEVEL
        1;
COMP "fpga_0_PushButtons_5Bit_GPIO_IO_pin<0>" LOCATE = SITE "AG5" LEVEL 1;
COMP "fpga_0_PushButtons_5Bit_GPIO_IO_pin<1>" LOCATE = SITE "AH4" LEVEL 1;
COMP "fpga_0_PushButtons_5Bit_GPIO_IO_pin<2>" LOCATE = SITE "AG3" LEVEL 1;
COMP "fpga_0_PushButtons_5Bit_GPIO_IO_pin<3>" LOCATE = SITE "AH1" LEVEL 1;
COMP "fpga_0_PushButtons_5Bit_GPIO_IO_pin<4>" LOCATE = SITE "AH2" LEVEL 1;
COMP "fpga_0_RS232_Uart_1_RX_pin" LOCATE = SITE "AJ8" LEVEL 1;
COMP "fpga_0_RS232_Uart_1_TX_pin" LOCATE = SITE "AE7" LEVEL 1;
COMP "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin" LOCATE = SITE "AG1"
        LEVEL 1;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_1.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_1.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_2.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_2.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_3.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_3.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_4.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_4.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_5.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_5.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_6.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_6.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_7.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_7.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_8.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_8.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_9.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_9.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_10.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_10.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_11.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_11.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_12.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_12.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_13.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_13.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_14.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_14.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_15.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_15.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_16.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_16.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_17.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_17.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_18.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_18.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_19.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_19.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_20.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_20.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_21.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_21.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_22.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_22.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_23.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_23.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_24.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_24.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_25.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_25.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_26.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_26.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_27.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_27.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_28.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_28.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_29.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_29.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_30.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_30.A"
        PINNAME CLKA;
PIN
        plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_31.A_pins<53>
        = BEL
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_31.A"
        PINNAME CLKA;
PIN ppc405_0/ppc405_0/PPC405_i_pins<172> = BEL "ppc405_0/ppc405_0/PPC405_i"
        PINNAME CPMC405CLOCK;
PIN ppc405_0/ppc405_0/PPC405_i_pins<421> = BEL "ppc405_0/ppc405_0/PPC405_i"
        PINNAME PLBCLK;
TIMEGRP dcm_0_dcm_0_CLK0_BUF = PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_0.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_1.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_2.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_3.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_4.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_5.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_6.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_7.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_8.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_9.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_10.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_11.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_12.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_13.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_14.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_15.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_16.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_17.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_18.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_19.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_20.A_pins<53>"
        PIN
        "plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s2_s2_21.A_pins<53>"
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