📄 myfirewall.c
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//////////////////////////////////////////////////////////////////////////////
// Filename: E:\fpga_fw/drivers/myfirewall_v1_00_a/src/myfirewall.c
// Version: 1.00.a
// Description: MYFIREWALL Driver Source File
// Date: Mon Mar 17 21:58:13 2008 (by Create and Import Peripheral Wizard)
//////////////////////////////////////////////////////////////////////////////
/***************************** Include Files *******************************/
#include "myfirewall.h"
//#include "xps2.h"
#include "myfirewall_reg.h"
/************************** Constant Definitions ****************************/
#define WR_DELAY 800 //about 10 clocks in MYFIREWALL
#define RD_DELAY 800 //about 20 clocks in MYFIREWALL
#define CLR_DELAY 400 //about 10 clocks in MYFIREWALL
#define ST_TIME 200000000 //about 5 seconds
/************************** Function Definitions ***************************/
/*****************************************************
SlaveReg0: bit0:ppc_ce_n_cc
bit1:ppc_we_n_cc
bit2:ppc_rd_n_cc
bit3:ppc_clr_n_cc
SlaveReg1: ppc_addr_cc
SlaveReg2: ppc_wdat_cc
SlaveReg3: cc_rdat_ppc
*****************************************************/
void MYFIREWALL_Write_Reg(Xuint32 BaseAddress, Xuint8 RegAddress, Xuint16 Reg_Value_Wr)
{
volatile int Delay;
//write the data to slavereg2
MYFIREWALL_mWriteSlaveReg2(BaseAddress, Reg_Value_Wr);
//write the address to slavereg1
MYFIREWALL_mWriteSlaveReg1(BaseAddress, RegAddress);
//write singal,clr:1,re:1,we:0,ce:0,1100
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x000C); //dplus comment for test
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x3000); //dplus
//xil_printf("%d %d %d %d\r\n",MYFIREWALL_mReadSlaveReg0(BaseAddress),MYFIREWALL_mReadSlaveReg1(BaseAddress),MYFIREWALL_mReadSlaveReg2(BaseAddress),MYFIREWALL_mReadSlaveReg3(BaseAddress));
//
for(Delay = 0; Delay < WR_DELAY; Delay++);
//clear the write singal
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x000F); //dplus comment for test
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0xf000); //dplus
}
Xuint16 MYFIREWALL_Read_Reg(Xuint32 BaseAddress, Xuint8 RegAddress)
{
volatile int Delay;
Xuint16 Reg_Data_Rd;
//write the address to slavereg1
MYFIREWALL_mWriteSlaveReg1(BaseAddress, RegAddress);
//read singal,clr:1,re:0,we:1,ce:0,1010
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x000A); //dplus comment for test
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x5000); //dplus
for(Delay = 0; Delay < RD_DELAY; Delay++);
//read the cc to ppc data
Reg_Data_Rd = MYFIREWALL_mReadSlaveReg3(BaseAddress);
//clear the read singal
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x000F); //dplus comment for test
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0xf000); //dplus comment for test
return Reg_Data_Rd;
}
void MYFIREWALL_Clear_Reg(Xuint32 BaseAddress)
{
volatile int Delay;
//clear singal,clr:0,re:1,we:1,ce:0,0110
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x0006);
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x6000);
for(Delay = 0; Delay < CLR_DELAY; Delay++);
//clear the read singal
//MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0x000F);
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0xF000);
}
void MYFIREWALL_Write_CAM(Xuint32 BaseAddress, Xuint32 Write_Data, Xuint8 Filter_Select, Xuint16 Addr_CAM)
{
switch(Filter_Select)
{
case 1:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, Write_Data);
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, 0x00);}
break;//0001b dp
case 2:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, 0x00);
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, Write_Data);}
break;//0010b sp
case 3:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, Write_Data); //dp
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, (Write_Data>>16));} //sp
break;//0011b dp & sp
case 4:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, Write_Data); //dip low
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, (Write_Data>>16));} //dip high
break;//0100b dip
case 8:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, Write_Data); //sip low
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, (Write_Data>>16)); //sip high
}break;//1000b sip
case 0:{MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_15_0, 0x0000);
MYFIREWALL_Write_Reg(BaseAddress, CI_DIN_CAM_31_16, 0x0000);
}break;
default : xil_printf("Wrong Selection");break;
}
MYFIREWALL_Write_Reg(BaseAddress, CI_WR_ADDR_CAM, Addr_CAM);
}
Xuint32 MYFIREWALL_Read_CAM(Xuint32 BaseAddress, Xuint16 Addr_CAM)
{
Xuint16 Data_High, Data_Low;
Xuint32 Read_Data;
Data_High = MYFIREWALL_Read_Reg(BaseAddress, CI_DIN_CAM_31_16);
Data_Low = MYFIREWALL_Read_Reg(BaseAddress, CI_DIN_CAM_15_0);
Read_Data = Data_High;
Read_Data = (Read_Data << 16);
Read_Data = Read_Data + Data_Low;
return Read_Data;
}
void MYFIREWALL_Write_Start_Time(Xuint32 BaseAddress, Xuint32 StartTime)
{
MYFIREWALL_Write_Reg(BaseAddress, TIME_31_16, (StartTime >> 16));
MYFIREWALL_Write_Reg(BaseAddress, TIME_15_0, (StartTime));
}
Xuint32 MYFIREWALL_Read_Start_Time(Xuint32 BaseAddress)
{
Xuint32 StartTime;
StartTime = MYFIREWALL_Read_Reg(BaseAddress, TIME_31_16);
StartTime = StartTime << 16;
StartTime += MYFIREWALL_Read_Reg(BaseAddress, TIME_15_0);
return StartTime;
}
void MYFIREWALL_Write_Byte_Counter(Xuint32 BaseAddress, Xuint32 Byte_Cnt)
{
Xuint16 temp;
MYFIREWALL_Write_Reg(BaseAddress, BYTE_CNT_26_11, (Byte_Cnt >> 11));
temp = MYFIREWALL_Read_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16);
temp = temp & 0x001F;
temp = temp + (Byte_Cnt & 0xFFFFFFE0);
MYFIREWALL_Write_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16, temp);
}
Xuint32 MYFIREWALL_Read_Byte_Counter(Xuint32 BaseAddress)
{
Xuint32 Byte_Cnt;
Xuint16 temp;
Byte_Cnt = MYFIREWALL_Read_Reg(BaseAddress, BYTE_CNT_26_11);
Byte_Cnt = Byte_Cnt << 11;
temp = MYFIREWALL_Read_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16);
temp = temp >>5;
Byte_Cnt = Byte_Cnt + temp;
Byte_Cnt = Byte_Cnt & 0X07FFFFFF;
return Byte_Cnt;
}
void MYFIREWALL_Write_Pkt_Counter(Xuint32 BaseAddress, Xuint32 Pkt_Cnt)
{
Xuint16 temp;
MYFIREWALL_Write_Reg(BaseAddress, PKT_CNT_15_0, Pkt_Cnt);
temp = MYFIREWALL_Read_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16);
temp = temp & 0xFFE0;
temp = temp + ((Pkt_Cnt >> 16) & 0x0000001F);
MYFIREWALL_Write_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16, temp);
}
Xuint32 MYFIREWALL_Read_Pkt_Counter(Xuint32 BaseAddress)
{
Xuint32 Pkt_Cnt;
Pkt_Cnt = MYFIREWALL_Read_Reg(BaseAddress, BYTE_CNT_10_0_PKT_CNT_20_16);
Pkt_Cnt = Pkt_Cnt << 16;
Pkt_Cnt = Pkt_Cnt + MYFIREWALL_Read_Reg(BaseAddress, PKT_CNT_15_0);
Pkt_Cnt = Pkt_Cnt & 0x001FFFFF;
return Pkt_Cnt;
}
void MYFIREWALL_Write_Current_Time(Xuint32 BaseAddress, Xuint32 Curt_Time)
{
MYFIREWALL_Write_Reg(BaseAddress, CURT_TIME_31_16, (Curt_Time >> 16));
MYFIREWALL_Write_Reg(BaseAddress, CURT_TIME_15_0, (Curt_Time));
}
Xuint32 MYFIREWALL_Read_Current_Time(Xuint32 BaseAddress)
{
Xuint32 Curt_Time;
Curt_Time = MYFIREWALL_Read_Reg(BaseAddress, CURT_TIME_31_16);
Curt_Time = Curt_Time << 16;
Curt_Time += MYFIREWALL_Read_Reg(BaseAddress, CURT_TIME_15_0);
return Curt_Time;
}
void MYFIREWALL_Write_MAC_Addr(Xuint32 BaseAddress, Xuint8 MAC_Addr0, Xuint8 MAC_Addr1, Xuint8 MAC_Addr2, Xuint8 MAC_Addr3, Xuint8 MAC_Addr4, Xuint8 MAC_Addr5)
{
Xuint16 MAC_Seg0, MAC_Seg1, MAC_Seg2;
MAC_Seg0 = MAC_Addr0;
MAC_Seg0 = MAC_Seg0 << 8;
MAC_Seg0 = (MAC_Seg0 & 0xFF00) + MAC_Addr1;
MAC_Seg1 = MAC_Addr2;
MAC_Seg1 = MAC_Seg1 << 8;
MAC_Seg1 = (MAC_Seg1 & 0xFF00) + MAC_Addr3;
MAC_Seg2 = MAC_Addr4;
MAC_Seg2 = MAC_Seg2 << 8;
MAC_Seg2 = (MAC_Seg2 & 0xFF00) + MAC_Addr5;
MYFIREWALL_Write_Reg(BaseAddress, TIEEMACCONFIGVEC_15_0, MAC_Seg0);
MYFIREWALL_Write_Reg(BaseAddress, TIEEMACCONFIGVEC_31_16, MAC_Seg1);
MYFIREWALL_Write_Reg(BaseAddress, TIEEMACCONFIGVEC_47_32, MAC_Seg2);
}
void MYFIREWALL_Read_MAC_Addr(Xuint32 BaseAddress, Xuint8 * MAC_Addr0, Xuint8 * MAC_Addr1, Xuint8 * MAC_Addr2, Xuint8 * MAC_Addr3, Xuint8 * MAC_Addr4, Xuint8 * MAC_Addr5)
{
Xuint16 MAC_Seg0, MAC_Seg1, MAC_Seg2;
MAC_Seg0 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_15_0);
MAC_Seg1 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_31_16);
MAC_Seg2 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_47_32);
(*MAC_Addr0) = (MAC_Seg0 >> 8);
(*MAC_Addr1) = MAC_Seg0;
(*MAC_Addr2) = (MAC_Seg1 >> 8);
(*MAC_Addr3) = MAC_Seg1;
(*MAC_Addr4) = (MAC_Seg2 >> 8);
(*MAC_Addr5) = MAC_Seg2;
}
void System_Initial(Xuint32 BaseAddress)
{
Xuint16 mac_reg_46_44;
xil_printf("-- System Start --\r\n");
xil_printf("-- System Initialization --\r\n");
//initialize the control register
MYFIREWALL_mWriteSlaveReg0(BaseAddress, 0xFFFF);
//configure the LEN_CAL module
MYFIREWALL_Write_Reg(BaseAddress, SHORT_PKT_SIZE, 48);
MYFIREWALL_Write_Reg(BaseAddress, LONG_PKT_SIZE, 1536);
xil_printf("The short packet size is %d\r\n", 48);
xil_printf("The long packet size is %d\r\n", 1536);
//configure the CAM
xil_printf("No filter rules are configuered in CAM\r\n");
//configure the result table
xil_printf("the result table is not configured\r\n");
//mac mask control
xil_printf("mac mask control is not configured\r\n");
//sample data
xil_printf("sample data is not configured\r\n");
//statistic select
xil_printf("statistic select is not configured\r\n");
//init_start register
MYFIREWALL_Write_Reg(BaseAddress, INIT_START, 0x0000);
xil_printf("init_start register is configured\r\n");
//the statistic information
//mac configure
//mac address
MYFIREWALL_Write_MAC_Addr(BaseAddress, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF);
MYFIREWALL_Write_Reg(BaseAddress, TIEEMACCONFIGVEC_63_48, 0x8F5E); //1000_1111_0101_1110b
mac_reg_46_44 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_66_64);
mac_reg_46_44 = mac_reg_46_44 & 0xFFF9;
MYFIREWALL_Write_Reg(BaseAddress, TIEEMACCONFIGVEC_66_64, mac_reg_46_44); //000b
xil_printf("initialization is done\r\n");
///dplus
Xuint16 MAC_Seg0,MAC_Seg1,MAC_Seg2;
MAC_Seg0 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_15_0);
MAC_Seg1 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_31_16);
MAC_Seg2 = MYFIREWALL_Read_Reg(BaseAddress, TIEEMACCONFIGVEC_47_32);
xil_printf("mac %d, %d, %d\r\n",MAC_Seg0,MAC_Seg1,MAC_Seg2);
}
void MYFIREWALL_Read_Hint()
{
xil_printf("Read HINT:\r\n");
xil_printf("The names of registers to be read and the corresponding input commands:\r\n");
xil_printf("Read SHORT_PKT_SIZE Please Input 1\r\n");
xil_printf(" LONG_PKT_SIZE 2\r\n");
xil_printf(" SHORT_PKT_CNT 3\r\n");
xil_printf(" LONG_PKT_CNT 4\r\n");
xil_printf(" CAM 5\r\n");
xil_printf(" RESULT_TABLE_CONTROL 6\r\n");
xil_printf(" Filter_Control 7\r\n");
xil_printf(" SAMPLE_DATA 8\r\n");
xil_printf(" STATISTIC_SELECT 9\r\n");
xil_printf(" INIT_START 10\r\n");
xil_printf(" PPC_READ_ADDR 11\r\n");
xil_printf(" START_TIME 12\r\n");
xil_printf(" BYTE_CNT 13\r\n");
xil_printf(" PKT_CNT 14\r\n");
xil_printf(" CURRENT_TIME 15\r\n");
xil_printf(" MAC_ADDRESS 16\r\n");
}
void MYFIREWALL_Write_Hint()
{
xil_printf("Write HINT:\r\n");
xil_printf("The names of registers to be written or write and the corresponding input commands:\r\n");
xil_printf("Write SHORT_PKT_SIZE Please Press 1\r\n");
xil_printf(" LONG_PKT_SIZE 2\r\n");
xil_printf(" SHORT_PKT_CNT 3\r\n");
xil_printf(" LONG_PKT_CNT 4\r\n");
xil_printf(" CAM 5\r\n");
xil_printf(" RESULT_TABLE_CONTROL 6\r\n");
xil_printf(" Filter_Control 7\r\n");
xil_printf(" SAMPLE_DATA 8\r\n");
xil_printf(" STATISTIC_SELECT 9\r\n");
xil_printf(" INIT_START 10\r\n");
xil_printf(" PPC_READ_ADDR 11\r\n");
xil_printf(" START_TIME 12\r\n");
xil_printf(" BYTE_CNT 13\r\n");
xil_printf(" PKT_CNT 14\r\n");
xil_printf(" CURRENT_TIME 15\r\n");
xil_printf(" MAC_ADDRESS 16\r\n");
}
void MYFIREWALL_Read_Operation(Xuint32 BaseAddress)
{
Xuint8 CMD_Signal;
Xuint16 Read_Value;
Xuint8 CAM_Address;
Xuint32 CAM_Data;
Xuint32 Start_Time;
Xuint32 Current_Time;
Xuint32 Byte_Cnt;
Xuint32 Pkt_Cnt;
Xuint8 MAC_Addr0;
Xuint8 MAC_Addr1;
Xuint8 MAC_Addr2;
Xuint8 MAC_Addr3;
Xuint8 MAC_Addr4;
Xuint8 MAC_Addr5;
/*Xuint16 MAC_Addr0;
Xuint16 MAC_Addr1;
Xuint16 MAC_Addr2;*/
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