tri_mode_eth_mac_v3_2_top.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//
//-----------------------------------------------------------------------------
// Title      : tri_mode_eth_mac_v2_2_top
// Project    : 
//-----------------------------------------------------------------------------
// File       : tri_mode_eth_mac_v2_2_top.v
// Author     : 
// Date       : 08-03-11
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1 ns/10 ps

module tri_mode_eth_mac_v3_2_top
(
sys_clk,
tx_clk,
reset,
tx_ll_data_in,
tx_ll_sof_in_n,
tx_ll_eof_in_n,
tx_ll_src_rdy_in_n,
tx_ll_dst_rdy_out_n,
rx_clk,
rx_ll_data_out,
rx_ll_sof_out_n,
rx_ll_eof_out_n,
rx_ll_src_rdy_out_n,
rx_ll_dst_rdy_in_n,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
gmii_crs,
gmii_col,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
pause_req,
pause_val,
conf_wr_mac,
conf_rd_mac,
conf_clr_mac,
conf_addr_mac,
conf_wdat_mac,
mac_rdat_conf
);

input  sys_clk;
input  tx_clk;
input  reset;
input [7:0] tx_ll_data_in;
input  tx_ll_sof_in_n;
input  tx_ll_eof_in_n;
input  tx_ll_src_rdy_in_n;
output tx_ll_dst_rdy_out_n;

input  rx_clk;
output [7:0] rx_ll_data_out;
output rx_ll_sof_out_n;
output rx_ll_eof_out_n;
output rx_ll_src_rdy_out_n;
input  rx_ll_dst_rdy_in_n;

output [7:0]     gmii_txd;
output   gmii_tx_en;
output    gmii_tx_er;
input    gmii_crs;
input    gmii_col;
input [7:0]   gmii_rxd;
input    gmii_rx_dv;
input    gmii_rx_er;

input  pause_req;
input  [15:0] pause_val; 

input   conf_wr_mac;
input   conf_rd_mac;
input   conf_clr_mac;
input  [3:0]    conf_addr_mac;
input  [15:0]   conf_wdat_mac;
output [15:0]   mac_rdat_conf;

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/

parameter D = 2;

/*-------------------------------------------------------------------*\
                          Register Wire Definition
\*-------------------------------------------------------------------*/
wire [7:0] rx_data;
wire rx_data_valid;
wire rx_good_frame;
wire rx_bad_frame;

wire [7:0] tx_data;
wire tx_data_valid;
wire tx_ack;
wire tx_underrun;
wire tx_collision;
wire tx_retransmit;

wire speedis10100_int;
wire speedis100_int;
reg  speedis10100;
reg rx_enable;
reg tx_enable;
reg [66:0] tieemacconfigvec;
reg [15:0] mac_rdat_conf;
/*-------------------------------------------------------------------*\
                                    main code
\*-------------------------------------------------------------------*/

always @(posedge rx_clk or posedge reset)
begin
  if (reset == 1'b1)
    speedis10100 <= #D 1'b0;
  else
    speedis10100 <= #D speedis10100_int;
end

always @(posedge rx_clk or posedge reset)
   begin
     if (reset == 1'b1)
       rx_enable <= #D 1'b0;
     else
       if (speedis10100 == 1'b1)
         rx_enable <= #D ~(rx_enable);
       else
         rx_enable <= #D 1'b1;
   end

always @(posedge tx_clk or posedge reset)
   begin
     if (reset == 1'b1)
       tx_enable <= #D 1'b0;
     else
       if (speedis10100 == 1'b1)
         tx_enable <= #D ~(tx_enable);
       else
         tx_enable <= #D 1'b1;
   end

tri_mode_eth_mac_v3_2 trimac_core( 
      .reset                     (reset),//input

      .emacphytxd                (gmii_txd),
      .emacphytxen               (gmii_tx_en),
      .emacphytxer               (gmii_tx_er),
      .phyemaccrs                (gmii_crs),
      .phyemaccol                (gmii_col),
      .phyemacrxd                (gmii_rxd),
      .phyemacrxdv               (gmii_rx_dv),
      .phyemacrxer               (gmii_rx_er),

//      .emacphymclkout            (mdio_clk),
//      .emacphymdtri              (mdio_tri),
//      .emacphymdout              (mdio_out),
//      .phyemacmdin               (mdio_in),

      .clientemactxd             (tx_data),
      .clientemactxdvld          (tx_data_valid),
      .emacclienttxack           (tx_ack),
      .clientemactxunderrun      (tx_underrun),
      .emacclienttxcollision     (tx_collision),
      .emacclienttxretransmit    (tx_retransmit),
      .clientemactxifgdelay      (8'b0),
      .clientemactxenable        (tx_enable),
      
      .clientemacpausereq        (pause_req),
      .clientemacpauseval        (pause_val),

      .emacclientrxd             (rx_data),
      .emacclientrxdvld          (rx_data_valid),
      .emacclientrxgoodframe     (rx_good_frame),
      .emacclientrxbadframe      (rx_bad_frame),
      .clientemacrxenable        (rx_enable),
       
      .emacclienttxstats         (),
      .emacclienttxstatsvld      (),

      .emacclientrxstats         (),
      .emacclientrxstatsvld      (),

      .txgmiimiiclk              (tx_clk),
      .rxgmiimiiclk              (rx_clk),
      .speedis100                (speedis100_int),
      .speedis10100              (speedis10100_int),
       
      .tieemacconfigvec          (tieemacconfigvec),

      .corehassgmii              (1'b0)
      );

  ten_100_1g_eth_fifo client_side_FIFo
    (.tx_clk                     (tx_clk),
     .tx_reset                   (reset),
     .tx_enable                  (tx_enable),
     .tx_data                    (tx_data),
     .tx_data_valid              (tx_data_valid),
     .tx_ack                     (tx_ack),
     .tx_underrun                (tx_underrun),
     .tx_collision               (tx_collision),
     .tx_retransmit              (tx_retransmit),

     .tx_ll_clock                (sys_clk),
     .tx_ll_reset                (reset),
     .tx_ll_data_in              (tx_ll_data_in),
     .tx_ll_sof_in_n             (tx_ll_sof_in_n),
     .tx_ll_eof_in_n             (tx_ll_eof_in_n),
     .tx_ll_src_rdy_in_n         (tx_ll_src_rdy_in_n),
     .tx_ll_dst_rdy_out_n        (tx_ll_dst_rdy_out_n),
     .tx_fifo_status             (),
     .tx_overflow                (),

     .rx_clk                     (rx_clk),
     .rx_reset                   (reset),
     .rx_enable                  (rx_enable),
     .rx_data                    (rx_data),
     .rx_data_valid              (rx_data_valid),
     .rx_good_frame              (rx_good_frame),
     .rx_bad_frame               (rx_bad_frame),
     .rx_overflow                (),
                                 
     .rx_ll_clock                (sys_clk),
     .rx_ll_reset                (reset),
     .rx_ll_data_out             (rx_ll_data_out),
     .rx_ll_sof_out_n            (rx_ll_sof_out_n),
     .rx_ll_eof_out_n            (rx_ll_eof_out_n),
     .rx_ll_src_rdy_out_n        (rx_ll_src_rdy_out_n),
     .rx_ll_dst_rdy_in_n         (rx_ll_dst_rdy_in_n),
     .rx_fifo_status             ()
     );

//configure the mac core
always @(posedge sys_clk or posedge reset)
begin
  if (reset == 1'b1)
    tieemacconfigvec[15:0] <= #D 16'b1;
  else if (conf_wr_mac && conf_addr_mac == 4'd0)
    tieemacconfigvec[15:0] <= #D conf_wdat_mac;
end

always @(posedge sys_clk or posedge reset)
begin
  if (reset == 1'b1)
    tieemacconfigvec[31:16] <= #D 16'b1;
  else if (conf_wr_mac && conf_addr_mac == 4'd1)
    tieemacconfigvec[31:16] <= #D conf_wdat_mac;
end

always @(posedge sys_clk or posedge reset)
begin
  if (reset == 1'b1)
    tieemacconfigvec[47:32] <= #D 16'b1;
  else if (conf_wr_mac && conf_addr_mac == 4'd2)
    tieemacconfigvec[47:32] <= #D conf_wdat_mac;
end

always @(posedge sys_clk or posedge reset)
begin
  if (reset == 1'b1)
    tieemacconfigvec[63:48] <= #D 16'b1000_1111_0101_1110;
  else if (conf_wr_mac && conf_addr_mac == 4'd3)
    tieemacconfigvec[63:48] <= #D conf_wdat_mac;
end

always @(posedge sys_clk or posedge reset)
begin
  if (reset == 1'b1)
    tieemacconfigvec[66:65] <= #D 2'b0;
  else if (conf_wr_mac && conf_addr_mac == 4'd4)
    tieemacconfigvec[66:65] <= #D conf_wdat_mac[2:1];
end

//always @(posedge sys_clk or posedge reset)
//begin
//  if (reset == 1'b1)
//    tieemacconfigvec[66:64] <= #D 3'b0;
//  else if (conf_wr_mac && conf_addr_mac == 4'd4)
//    tieemacconfigvec[66:64] <= #D conf_wdat_mac[2:0];
//end

//47：0 MAC地址
//63：48  1000_1111_0101_1110
//66：64  000或者001

always @(posedge sys_clk or posedge reset)
begin
  if(reset) 
     mac_rdat_conf <= #D 16'b0;
  else if(conf_rd_mac)
  begin
    case(conf_addr_mac)
    4'd0:    mac_rdat_conf <= #D tieemacconfigvec[15:0];
    4'd1:    mac_rdat_conf <= #D tieemacconfigvec[31:16];
    4'd2:    mac_rdat_conf <= #D tieemacconfigvec[47:32];
    4'd3:    mac_rdat_conf <= #D tieemacconfigvec[63:48];
    4'd4:    mac_rdat_conf <= #D {13'b0,tieemacconfigvec[66:65],1'b0};
    default: mac_rdat_conf <= #D 16'b0;
    endcase
  end
end

endmodule