fw_top.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//
//-----------------------------------------------------------------------------
// Title      : The user logic top
// Project    : 
//-----------------------------------------------------------------------------
// File       : top.v
// Author     : 
// Date       : 08-03-11
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module fw_top(
sys_clk_in_100m,
sys_rst_n_in,
MAC_slew1,
MAC_slew2,
MAC_PHY_rst_n,

//ppc_ce_n_conf,
//ppc_we_n_conf,
//ppc_re_n_conf,
//ppc_clr_n_conf,
//ppc_addr_conf,
//ppc_wdat_conf,
//conf_rdat_ppc,

gmii_txd,
gmii_tx_en,
gmii_tx_er,
gmii_tx_clk,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
gmii_rx_clk,
gmii_col,
gmii_crs,


fpga_0_RS232_Uart_1_RX_pin, 
fpga_0_RS232_Uart_1_TX_pin, 
fpga_0_LEDs_4Bit_GPIO_IO_pin, 
fpga_0_DIPSWs_4Bit_GPIO_IO_pin, 
fpga_0_PushButtons_5Bit_GPIO_IO_pin, 
fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin, 
fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin, 
fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin, 
fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin,   
fpga_0_net_gnd_pin , 
fpga_0_net_gnd_1_pin,
fpga_0_net_gnd_2_pin,
fpga_0_net_gnd_3_pin,
fpga_0_net_gnd_4_pin,
fpga_0_net_gnd_5_pin,
fpga_0_net_gnd_6_pin





);

parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//Global Signals
input             sys_clk_in_100m;
input             sys_rst_n_in;

output           MAC_slew1;
output           MAC_slew2;
output           MAC_PHY_rst_n;

output [7:0]     gmii_txd;
output           gmii_tx_en;
output           gmii_tx_er;
input            gmii_tx_clk;
input  [7:0]     gmii_rxd;
input            gmii_rx_dv;
input            gmii_rx_er;
input            gmii_rx_clk;
input            gmii_col;
input            gmii_crs;

input  fpga_0_RS232_Uart_1_RX_pin; 
output fpga_0_RS232_Uart_1_TX_pin; 
inout [3:0] fpga_0_LEDs_4Bit_GPIO_IO_pin; 
inout [3:0] fpga_0_DIPSWs_4Bit_GPIO_IO_pin; 
inout [4:0] fpga_0_PushButtons_5Bit_GPIO_IO_pin; 
inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin; 
inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin; 
inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin;
inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin;  
output fpga_0_net_gnd_pin ; 
output fpga_0_net_gnd_1_pin;
output fpga_0_net_gnd_2_pin;
output fpga_0_net_gnd_3_pin;
output fpga_0_net_gnd_4_pin;
output fpga_0_net_gnd_5_pin;
output fpga_0_net_gnd_6_pin;

wire            ppc_ce_n_conf;    //ppc  chip enable signal to conf
wire            ppc_we_n_conf;    //ppc  write enable signal to conf
wire             ppc_re_n_conf;    //ppc  read enable signal to conf
wire            ppc_clr_n_conf;   //ppc  clear singal to conf
wire [7:0]      ppc_addr_conf;    //ppc  write address to conf
wire  [15:0]     ppc_wdat_conf;    //ppc  write data to conf
wire [15:0]     conf_rdat_ppc;    //conf read data to ppc
/*-------------------------------------------------------------------*\
                            wire Description
\*-------------------------------------------------------------------*/ 
reg              sys_clk;
wire              sys_clk_100m;
wire              sys_rst_n;
wire              rd_dst_rdy_n;
wire              pre_sop_key;
wire              pre_eop_key;
wire              pre_dvld_key;
wire   [31:0]     pre_dat_key;
wire   [1:0]      pre_mod_key;
wire              key_pb_pre;   
wire              conf_wr_cal;     
wire              conf_rd_cal;    
wire              conf_clr_cal;   
wire   [15:0]     cal_rdat_conf;
wire              key_sop_drop;
wire              key_eop_drop; 
wire  [31:0]      key_dat_drop;
wire  [1:0]       key_mod_drop;
wire              key_dvld_drop;  
wire              drop_pb_key;  
wire              key_sok_ci;
wire              key_eok_ci;
wire  [31:0]      key_key_ci;
wire              key_kvld_ci;
wire   [31:0]         ci_din_cam;
wire   [31:0]         ci_cmp_din_cam;
wire                   ci_en_cam;
wire                   ci_we_cam;
wire   [7:0]           ci_wr_addr_cam;
wire                   cam_busy_ci;
wire                   cam_match_ci;
wire   [7:0]           cam_match_addr_ci;
wire                   ci_vld_drop;
wire                   ci_drp_drop;
wire   [7:0]           ci_addr_drop;
wire   [3:0]           ci_dat_drop;
wire                   conf_wr_ci;
wire                   conf_rd_ci;
wire                   conf_clr_ci;
wire   [15:0]          ci_rdat_conf;
wire                   conf_wr_fs;
wire                   conf_rd_fs;
wire                   conf_clr_fs;
wire   [15:0]          fs_rdat_conf;
wire   [7:0]        wr_data;
wire                wr_sof_n;
wire                wr_eof_n;
wire                wr_src_rdy_n;
wire                wr_dst_rdy_n;
wire                conf_wr_drop;   
wire                conf_rd_drop;    
wire                conf_clr_drop;   
wire   [15:0]       drop_rdat_conf;

wire                fs_sop_key;
wire                fs_eop_key;
wire [31:0]         fs_dat_key;
wire [1:0]          fs_mod_key;
wire                fs_dvld_key;
wire                key_pb_fs;

//wire   [15:0]       mac_rdat_conf;
wire   [15:0]       conf_wdat;
wire   [3:0]        conf_addr;
wire   [31:0]      ci_cmp_dmsk_cam;

wire   [7:0]     rd_data_out;   
wire             rd_sof_n;      
wire             rd_eof_n;      
wire             rd_src_rdy_n;   

wire   [7:0]     gmii_txd_out;
wire             gmii_tx_en_out;
wire             gmii_tx_er_out;

wire conf_wr_mac;
wire conf_rd_mac;
wire conf_clr_mac;
wire  [15:0] mac_rdat_conf;

wire [7:0] gmii_rxd_ibuf;
wire gmii_rx_dv_ibuf;
wire gmii_rx_er_ibuf;
wire gmii_col_ibuf;
wire gmii_crs_ibuf;
wire MAC_slew1;
wire MAC_slew2;
wire MAC_PHY_rst_n;
wire reset;


wire fpga_0_RS232_Uart_1_RX_pin; 
wire fpga_0_RS232_Uart_1_TX_pin; 
wire [3:0] fpga_0_LEDs_4Bit_GPIO_IO_pin; 
wire [3:0] fpga_0_DIPSWs_4Bit_GPIO_IO_pin; 
wire [4:0] fpga_0_PushButtons_5Bit_GPIO_IO_pin; 
wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin; 
wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin; 
wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin;
wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin;  
wire fpga_0_net_gnd_pin ; 
wire fpga_0_net_gnd_1_pin;
wire fpga_0_net_gnd_2_pin;
wire fpga_0_net_gnd_3_pin;
wire fpga_0_net_gnd_4_pin;
wire fpga_0_net_gnd_5_pin;
wire fpga_0_net_gnd_6_pin;


/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/

tri_mode_eth_mac_v3_2_top u_tri_mode_eth_mac_v3_2_top(
         .sys_clk               (sys_clk),
         .tx_clk                (gmii_tx_clk),
         .reset                 (reset),
         .tx_ll_data_in         (wr_data[7:0]),
         .tx_ll_sof_in_n        (wr_sof_n),
         .tx_ll_eof_in_n        (wr_eof_n),
         .tx_ll_src_rdy_in_n    (wr_src_rdy_n),
         .tx_ll_dst_rdy_out_n   (wr_dst_rdy_n),

         .rx_clk                (gmii_rx_clk),
         .rx_ll_data_out        (rd_data_out[7:0]),
         .rx_ll_sof_out_n       (rd_sof_n),
         .rx_ll_eof_out_n       (rd_eof_n),
         .rx_ll_src_rdy_out_n   (rd_src_rdy_n),
         .rx_ll_dst_rdy_in_n    (rd_dst_rdy_n),
         
         .gmii_txd              (gmii_txd_out),
         .gmii_tx_en            (gmii_tx_en_out),
         .gmii_tx_er            (gmii_tx_er_out),
         .gmii_crs              (gmii_crs_ibuf),
         .gmii_col              (gmii_col_ibuf),
         .gmii_rxd              (gmii_rxd_ibuf),
         .gmii_rx_dv            (gmii_rx_dv_ibuf),
         .gmii_rx_er            (gmii_rx_er_ibuf),
         
         .pause_req             (1'b0),
         .pause_val             (16'b0),
         
         .conf_wr_mac           (conf_wr_mac),
         .conf_rd_mac           (conf_rd_mac),
         .conf_clr_mac          (conf_clr_mac),
         .conf_addr_mac         (conf_addr[3:0]),
         .conf_wdat_mac         (conf_wdat[15:0]),
         .mac_rdat_conf         (mac_rdat_conf[15:0])
);

pre_prcs_top u_pre_prcs_top(
         .rx_clk            (sys_clk),
         .sys_clk           (sys_clk),
         .sys_rst_n         (sys_rst_n),
         .rd_data_out       (rd_data_out[7:0]),
         .rd_sof_n          (rd_sof_n),
         .rd_eof_n          (rd_eof_n),
         .rd_src_rdy_n      (rd_src_rdy_n),
         .rd_dst_rdy_n      (rd_dst_rdy_n),
         .rx_fifo_status    (4'b0),