lb_fifo_cell.v

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// $Id: lb_fifo_cell.v,v 1.1 2006-02-26 17:11:50-08 mzeng Exp $
/*******************************************************************************
//
//  Author:    Hongjian Ye
//  Filename:  lb_fifo_cell.v
//  Modified:  02/28/00
//
//  Description: FIFO data buffer Cell;
//
//  Modification History:
//
//  Date      Who      Description of change
//  ------------------------------------------------------------------------
//  02/00/00  Hongjian
//
//  ------------------------------------------------------------------------
//                   Copyright (c) 2000 Nexware Corp.
//                   All rights reserved
*******************************************************************************/
 
module  lb_fifo_cell
    (   sys_clk,
        sys_rst_n,

        data_in,
        data_write,

        next_data,
        next_full,
        last_full,

        data_out,
        data_read,

        full
    );
 
    parameter   WIDTH = 8;
    parameter   D       = 2;
 
////////////////////////////////////////
////    Global signals
////////////////////////////////////////
    input                   sys_clk;        // Internal system clk;
    input                   sys_rst_n;        // synopsys sync_set_reset "sys_rst_n"

    input    [WIDTH-1:0]    data_in;        // Data that is pushing in;
    input    [WIDTH-1:0]    next_data;      // Next cell buffered data;
    output   [WIDTH-1:0]    data_out;       // Current cell buffered data;

    input                   data_read;      // Buffer read;
    input                   data_write;     // Buffer push;

    output                  full;           // Current cell full;
    input                   next_full;      // Next cell full;
    input                   last_full;      // Last cell full;

 
    reg      [WIDTH-1:0]     data_out;
    reg      [WIDTH-1:0]     data_ld;
    reg                      full;
    reg                      full_next;
    reg                      fc_ld;

    always @(posedge sys_clk or negedge sys_rst_n )
        if(!sys_rst_n)
            data_out[WIDTH-1:0] <= #D 0;
        else if (fc_ld)
            data_out[WIDTH-1:0] <= #D data_ld[WIDTH-1:0];

	always @ (data_write or data_read or full or last_full)
	  casex ({data_write,data_read,full,last_full})
		4'bx1_xx : fc_ld = 1'b1;
		4'b10_01 : fc_ld = 1'b1;
	   default   : fc_ld = 1'b0;
	  endcase

	always @ (data_write or data_read or next_full or full or last_full
				or data_in or next_data)
	  casex ({data_write,data_read,next_full,full,last_full})
		5'b10_x01 : data_ld[WIDTH-1:0] = data_in[WIDTH-1:0];
		5'b11_01x : data_ld[WIDTH-1:0] = data_in[WIDTH-1:0];
		default   : data_ld[WIDTH-1:0] = next_data[WIDTH-1:0];
	  endcase

    always @(posedge sys_clk or negedge sys_rst_n )
        if(!sys_rst_n)
            full <= #D 0;
        else if (data_write || data_read)
            full <= #D full_next;
            
    always @(data_write or data_read or next_full or last_full or full)
        casex ({data_write,data_read})
          2'b00 : full_next = full;
          2'b01 : full_next = next_full;
          2'b10 : full_next = last_full;
          2'b11 : full_next = full;
         endcase
    
endmodule