tx_client_fifo.v

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//-----------------------------------------------------------------------------
// Title      : Client to Local-link Transmitter FIFO
// Project    : Tri-Mode Ethernet MAC
//-----------------------------------------------------------------------------
// File       : tx_client_fifo.v
// Author     : Xilinx
//-----------------------------------------------------------------------------
// Copyright (c) 2004-2005 by Xilinx, Inc. All rights reserved.
// This text/file contains proprietary, confidential
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// a license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
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// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
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//
// This copyright and support notice must be retained as part
// of this text at all times. (c) Copyright 2004-2005 Xilinx, Inc.
// All rights reserved.
//------------------------------------------------------------------------
// Description: This is a transmitter side local link fifo implementation for
//              the client loopback desing example of the Tri-Mode Ethernet MAC core
//
//              The transmit FIFO is created from 2 Block RAMs of size 2048
//              words of 9-bits per word, giving a total frame memory capacity
//              of 4096 bytes.
//
//              Valid frame data received from local link interface is written
//              into the Block RAM on the write_clock.  The FIFO will store
//              frames upto 4kbytes in length.  If larger frames are written
//              to the FIFO the local-link interface will accept the rest of the
//              frame, but that frame will be dropped by the FIFO, and is
//              indicated as such by the assertion of overflow.  The FIFO is
//              designed to work with a minimum total frame length of 14 bytes,
//              (6 byte Destination Addr, 6 byte Source Addr, 2 byte
//              Length/Type field).
//              
//              When there is at least one complete frame in the FIFO,
//              the MAC transmitter client interface will be driven to
//              request frame transmission by placing the first byte of
//              the frame onto tx_data[7:0] and by asserting
//              tx_data_valid.  The MAC will later respond by asserting
//              tx_ack.  At this point the remaining frame data is read
//              out of the FIFO in a continuous burst. Data is read out
//              of the FIFO on the tx_clk.
//
//              If FULL_DUPLEX_ONLY is defined, the FIFO will
//              requeue and retransmit frames as requested by the MAC.  Once a
//              frame has been transmitted by the FIFO it is stored until the
//              possible retransmit window for that frame has expired.  This is
//              determined by either the next frame being accepted for
//              transmission or the delay from the last transmission being
//              enough to assume no further collisions can occur.
//
//              The FIFO memory size can be increased by expanding the tx_addr
//              and write_addr signal widths, to address further BRAMs.
//              Control signals can be modified as commented in the FIFO
//              architecture.  Look for ** comments.


`timescale 1ps / 1ps

module tx_client_fifo
     (
        // MAC Interface
        tx_clk,
        tx_reset,
        tx_enable,
        tx_data,
        tx_data_valid,
        tx_ack,
        tx_underrun,
        tx_collision,
        tx_retransmit,
        overflow,
        
        // Local-link Interface
        write_clock_in,
        ll_reset,
        data_in,
        rem_in,
        sof_in_n,
        eof_in_n,
        src_rdy_in_n,
        dst_rdy_out_n,
        fifo_status_out
     );

  
  //-----------------------------------------------------------------------------
  // Define Interface Signals
  //-----------------------------------------------------------------------------
  // MAC Interface
   input        tx_clk;
   input        tx_reset;
   input        tx_enable;
   output [7:0] tx_data;
   output       tx_data_valid;
   input        tx_ack;
   output       tx_underrun;
   input        tx_collision;
   input        tx_retransmit;
   output       overflow;
        
   // Local-link Interface
   input        write_clock_in;
   input        ll_reset;
   input  [7:0] data_in;
   input  [0:0] rem_in;
   input        sof_in_n;
   input        eof_in_n;
   input        src_rdy_in_n;
   output       dst_rdy_out_n;
   output [3:0] fifo_status_out;

   
  //-----------------------------------------------------------------------------
  // Define Internal Signals
  //-----------------------------------------------------------------------------
  // Local link side data signals.
  reg  [7:0] data_in_reg;
  reg        eof_in_n_reg;
  reg        eof_in_n_reg_reg;
  reg        eof_in_n_reg_reg_reg;
  wire [0:0] data_valid_reg;
  reg        write_data_valid_reg;
  wire       write_data_valid;
  reg        write_data_valid_int;
  reg        overflow_eof_in_n_reg;
  reg        overflow_eof_in_n_reg_reg;
  reg        overflow_eof_in_n_reg_reg_reg;

  // Local link side control signals.
  wire       write_addr_enable;
  reg        frame_received;
  reg 	     ll_frame_transmitted;
  reg        ll_frame_retransmit;
  reg  [2:0] ll_frame_transmitted_toggle;
  reg  [2:0] ll_frame_retransmit_toggle;
  wire       write_mem_enable;
  wire       write_mem_enable_l;
  wire       write_mem_enable_u;
  wire       overflow_accept;
  wire       byte_accept;

  // Client side data signals
  wire [7:0] tx_data_int;
  wire [7:0] tx_data_int_l;
  wire [7:0] tx_data_int_u;
  wire       tx_data_valid_int;
  reg  [7:0] tx_data_pipe; 
  reg        tx_data_valid_pipe;
  reg        tx_data_valid_reg;
  
  // Client side control signals.
  wire       tx_addr_enable;
  reg        tx_addr_enable_reg;
  wire [0:0] tx_dv_dv_l;
  wire [0:0] tx_dv_dv_u;
  reg        frame_in_progress;
  reg        queue;
  reg        frame_transmitted_toggle;
  reg 	     frame_retransmit_toggle;
  wire       tx_mem_enable;
  wire       tx_mem_enable_u;
  wire       tx_mem_enable_l;
  wire	     not_frame_in_progress;
`ifdef FULL_DUPLEX_ONLY
  wire       col_no_retransmit;
  wire       tx_retransmit_reg;
  wire       tx_retransmit_reg_reg;
  wire       tx_retransmit_reg_reg_reg;
  wire       queue_for_retransmit;
  wire       queue_for_retransmit_held;
  wire       retransmit_fip;
  wire       tx_collision_reg;
  wire [9:0] tx_length_count;
  wire [9:0] tx_idle_count;
`else
  reg        col_no_retransmit;
  reg        tx_retransmit_reg;
  reg        tx_retransmit_reg_reg;
  reg        tx_retransmit_reg_reg_reg;
  reg        queue_for_retransmit;
  reg        queue_for_retransmit_held;
  reg        retransmit_fip;
  reg        tx_collision_reg;
  reg  [9:0] tx_length_count;
  reg  [9:0] tx_idle_count;
`endif
  reg [10:0] tx_length_count_plus_tx_idle_count;

  // Fifo status signals
  wire [11:0] fifo_status_full;
  wire        frame_in_fifo;
  reg         frame_in_fifo_held;
  reg         overflow_int;
  wire        memory_full_pulse;
  reg         memory_full;
  reg         overflow_int_held;
  reg  [8:0]  frame_count;
  reg  [8:0]  frame_count_gray;
  reg  [8:0]  ll_frame_count;
  reg  [8:0]  ll_frame_count_gray;
  wire        full_pulse;
 
  // Client side address signals.
  wire [11:0] tx_addr;
  reg  [11:0] tx_addr_int;
  reg  [11:0] tx_addr_int_plus;
  reg  [11:0] tx_addr_reg;
  reg  [11:0] tx_addr_gray;
  reg  [11:0] tx_start_addr;
  reg  [11:0] tx_start_addr_gray;

  // Local link side address signals.
  wire [11:0] write_addr;
  reg [11:0] write_addr_int;
  reg [11:0] write_addr_reg;
  reg [11:0] ll_tx_addr_gray;
  reg [11:0] ll_tx_addr_bin;
  reg [11:0] start_addr;
  reg [11:0] ll_tx_start_addr_gray;
  reg [11:0] ll_tx_start_addr;
  reg [11:0] ll_add_sub;
  reg [11:0] ll_start_add_sub;

  wire       GND;
  wire       VCC;
  wire [7:0] GND_BUS;

  // ASYNC_REG attributes added to simulate actual behaviour under
  // asynchronous operating conditions.
  // synthesis attribute ASYNC_REG of ll_tx_addr_gray   is "TRUE";
  // synthesis attribute ASYNC_REG of ll_tx_start_addr_gray       is "TRUE";
  // synthesis attribute ASYNC_REG of frame_count_gray            is "TRUE";
  // synthesis attribute ASYNC_REG of ll_frame_transmitted_toggle is "TRUE";
  // synthesis attribute ASYNC_REG of ll_frame_retransmit_toggle  is "TRUE";
  
  // Small delay for simulation purposes.
  // constant dly : time := 1 ps;

 

 
  assign GND         = 1'b0;
  assign VCC         = 1'b1;
  assign GND_BUS     = 8'h00;
  assign tx_underrun = 1'b0;

  //---------------------------------------------------------------------------
  // Register the Input signals from the local link interface.
  //---------------------------------------------------------------------------
  always @(posedge write_clock_in)
  begin
    if (ll_reset == 1'b1)
      begin
      data_in_reg        <= 8'h00;     
      eof_in_n_reg       <= 1'b1;
      end
    else if (byte_accept == 1'b1)
      begin
      data_in_reg        <= data_in;
      eof_in_n_reg       <= eof_in_n;
      end
  end

  // register eof signals further for use in fifo control
  always @(posedge write_clock_in)
  begin
    if (ll_reset == 1'b1)
      begin
      eof_in_n_reg_reg      <= 1'b1;
      eof_in_n_reg_reg_reg  <= 1'b1;
      end
    else
      begin
      eof_in_n_reg_reg      <= eof_in_n_reg;
      eof_in_n_reg_reg_reg  <= eof_in_n_reg_reg;
      end
  end

  // construct data valid signal to indicate valid data within a frame
  // write_data_valid_int is high from the clk after sof until clk after eof
  // write_data_valid_reg is registered value of write_data_valid
  always @(posedge write_clock_in)
  begin
    if (ll_reset == 1'b1)
      write_data_valid_int    <= 1'b0;
    else
      begin
      if (byte_accept == 1'b1 && sof_in_n == 1'b0)
        write_data_valid_int <= 1'b1;
      else if (byte_accept == 1'b1 && eof_in_n == 1'b0)
        write_data_valid_int <= 1'b0;
      end
  end

  always @(posedge write_clock_in)
  begin
    if (ll_reset == 1'b1)
      write_data_valid_reg    <= 1'b0;
    else
      write_data_valid_reg    <= write_data_valid;
   end

  // write_data_valid indicates when each incoming byte represents valid frame
  // data.  
  assign write_data_valid = byte_accept & (write_data_valid_int | !(sof_in_n));