cam.xco

本系统由服务器软件控制平台和fpga硬件处理系统组成

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = False
SET verilogsim = True
SET workingdirectory = C:\my_projec\firewall
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = Verilog
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Content_Addressable_Memory family Xilinx,_Inc. 5.1
# END Select
# BEGIN Parameters
CSET read_warning_flag=false
CSET address_resolution=lowest
CSET memory_type=srl16e
CSET match_address_type=binary_encoded
CSET depth=256
CSET data_width=32
CSET multiple_match_flag=false
CSET register_outputs=false
CSET ternary_mode=ternary_mode_standard
CSET enable=true
CSET component_name=cam
CSET read_only_cam=false
CSET simultaneous_read_write=true
CSET single_match_flag=false
CSET load_initialization_file=false
# END Parameters
GENERATE