lb_fifo_4cell.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

// $Id: lb_fifo_4cell.v,v 1.1 2006-02-26 17:11:49-08 mzeng Exp $
/*******************************************************************************
//
//  Author:    Hongjian Ye
//  Filename:  lb_fifo_4cell.v
//  Modified:  02/28/00
//
//  Description: Data FIFO with 4 buffer Cells;
//
//  Modification History:
//
//  Date      Who      Description of change
//  ------------------------------------------------------------------------
//  02/00/00  Hongjian
//
//  ------------------------------------------------------------------------
//                   Copyright (c) 2000 Nexware Corp.
//                   All rights reserved
*******************************************************************************/

module  lb_fifo_4cell
    (   sys_clk,
        sys_rst_n,

        data_in,
        data_write,

        data_out,
        data_read,

        full_cell0,
        full_cell1,
        full_cell2,
        full_cell3
    );

    parameter   WIDTH = 8;
    parameter   D     = 2;
////////////////////////////////////////
////    Global signals
////////////////////////////////////////
    input                 sys_clk;        // Internal system clk;
    input                 sys_rst_n;        // synopsys sync_set_reset "sys_rst_n"

    input    [WIDTH-1:0]  data_in;        // Data that is pushing in;
    output   [WIDTH-1:0]  data_out;       // Data that is ready for read;;

    input                 data_read;      // Read from FIFO;
    input                 data_write;     // Write to FIFO;

    output                full_cell0;
    output                full_cell1;
    output                full_cell2;
    output                full_cell3;

    wire     [WIDTH-1:0]  data_cell0;
    wire     [WIDTH-1:0]  data_cell1;
    wire     [WIDTH-1:0]  data_cell2;
    wire     [WIDTH-1:0]  data_cell3;
    wire     [WIDTH-1:0]  data_cell4;

    wire                  full_cell4;


    lb_fifo_cell #( WIDTH,D ) cell0
      (  .sys_clk     ( sys_clk ),
         .sys_rst_n     ( sys_rst_n ),

         .data_in     ( data_in[WIDTH-1:0] ),
         .data_write  ( data_write ),

         .next_data   ( data_cell1[WIDTH-1:0] ),
         .next_full   ( full_cell1 ),
         .last_full   ( 1'b1 ),

         .data_out    ( data_out[WIDTH-1:0] ),
         .data_read   ( data_read ),

         .full        ( full_cell0 )
      );

    lb_fifo_cell #( WIDTH,D ) cell1
      (  .sys_clk     ( sys_clk ),
         .sys_rst_n     ( sys_rst_n ),

         .data_in     ( data_in[WIDTH-1:0] ),
         .data_write  ( data_write ),

         .next_data   ( data_cell2[WIDTH-1:0] ),
         .next_full   ( full_cell2 ),
         .last_full   ( full_cell0 ),

         .data_out    ( data_cell1[WIDTH-1:0] ),
         .data_read   ( data_read ),

         .full        ( full_cell1 )
      );

    lb_fifo_cell #( WIDTH,D ) cell2
      (  .sys_clk     ( sys_clk ),
         .sys_rst_n     ( sys_rst_n ),

         .data_in     ( data_in[WIDTH-1:0] ),
         .data_write  ( data_write ),

         .next_data   ( data_cell3[WIDTH-1:0] ),
         .next_full   ( full_cell3 ),
         .last_full   ( full_cell1 ),

         .data_out    ( data_cell2[WIDTH-1:0] ),
         .data_read   ( data_read ),

         .full        ( full_cell2 )
      );

    lb_fifo_cell #( WIDTH,D ) cell3
      (  .sys_clk     ( sys_clk ),
         .sys_rst_n     ( sys_rst_n ),

         .data_in     ( data_in[WIDTH-1:0] ),
         .data_write  ( data_write ),

         .next_data   ( data_cell4[WIDTH-1:0] ),
         .next_full   ( full_cell4 ),
         .last_full   ( full_cell2 ),

         .data_out    ( data_cell3[WIDTH-1:0] ),
         .data_read   ( data_read ),

         .full        ( full_cell3 )
      );

    assign  data_cell4[WIDTH-1:0] = {WIDTH{1'b0}};
    assign  full_cell4 = 1'b0;

endmodule