key_gen.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//generate search key
//-----------------------------------------------------------------------------
// Title      : 
// Project    : 
//-----------------------------------------------------------------------------
// File       : key_gen.v
// Author     : 
// Date       : 07-10-29
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module key_gen(
sys_clk,
sys_rst_n,
pre_sop_key,
pre_eop_key,
pre_dat_key, 
pre_mod_key,
pre_dvld_key,
key_pb_pre,
key_sop_drop,
key_eop_drop,
key_dat_drop,
key_mod_drop,
key_dvld_drop,
drop_pb_key,
key_sok_ci,
key_eok_ci,
key_key_ci,
key_kvld_ci
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/

parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//global signal
input                sys_clk;
input                sys_rst_n;

//interface with pre
input                pre_sop_key;
input                pre_eop_key;
input     [31:0]     pre_dat_key;
input     [1:0]      pre_mod_key;
input                pre_dvld_key;
output               key_pb_pre;

//interface with drop
output               key_sop_drop;
output               key_eop_drop;
output   [31:0]      key_dat_drop;
output    [1:0]      key_mod_drop;
output               key_dvld_drop;
input                drop_pb_key;

//interface with cam_if
output               key_sok_ci;
output               key_eok_ci;
output   [31:0]      key_key_ci;
output               key_kvld_ci;
/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg            key_pb_pre;
reg            key_sop_drop; 
reg            key_eop_drop; 
reg  [31:0]    key_dat_drop; 
reg   [1:0]    key_mod_drop; 
reg            key_dvld_drop;  
reg   [2:0]    eth_cnt;
reg   [7:0]    ip_cnt;
reg   [3:0]    ip_hlen;
reg            tu_flag;
reg   [5:0]    tu_cnt;
reg            key_sok_ci;
reg            key_eok_ci;
reg   [7:0]    ip_tos;
reg   [15:0]   tmp_sd;
reg   [31:0]   key_key_ci;
reg            key_kvld_ci;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/                           

//send push back to pre
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      key_pb_pre <= #D 1'b0;
   else
      key_pb_pre <= #D drop_pb_key;
end

//send packe t topacket and drop
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      begin
        key_sop_drop  <= #D 1'b0;
        key_eop_drop  <= #D 1'b0;
        key_dat_drop  <= #D 32'b0;
        key_mod_drop  <= #D 2'b0;
        key_dvld_drop <= #D 1'b0;
      end
   else
      begin
        key_sop_drop  <= #D pre_sop_key;
        key_eop_drop  <= #D pre_eop_key;
        key_dat_drop  <= #D pre_dat_key;
        key_mod_drop  <= #D pre_mod_key;
        key_dvld_drop <= #D pre_dvld_key;
      end
end

//generate key
//ethnet,ip and tcp/udp count for extraction
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      eth_cnt <= #D 3'h0;
   else if(pre_sop_key && pre_dvld_key)
      eth_cnt <= #D 3'h1;
   else if(&eth_cnt)
      eth_cnt <= #D eth_cnt;
   else if(pre_dvld_key)
      eth_cnt <= #D eth_cnt + 3'h1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ip_cnt <= #D 8'h80;
   else if(pre_dvld_key && eth_cnt == 3'h2)
      ip_cnt <= #D 8'h1;
   else if(ip_cnt[7])
      ip_cnt <= #D ip_cnt;
   else if(pre_dvld_key)
      ip_cnt <= #D ip_cnt << 1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ip_hlen <= #D 4'h0;
   else if(ip_cnt[0] && pre_dvld_key)
      ip_hlen <= #D 4'h5;
   else if(pre_dvld_key && |ip_hlen)
      ip_hlen <= #D ip_hlen - 4'h1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      tu_flag <= #D 1'b0;
   else if(pre_eop_key && pre_dvld_key)
      tu_flag <= #D 1'b0;
   else if(ip_cnt[2] && pre_dvld_key && pre_dat_key[7:0]== 8'h6)
      tu_flag <= #D 1'b1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      tu_cnt <= #D 6'b10_0000;
   else if(ip_hlen == 4'h2 && pre_dvld_key)
      tu_cnt <= #D 6'b00_0001;
   else if(tu_cnt[5])
      tu_cnt <= #D tu_cnt;
   else if(pre_dvld_key)
      tu_cnt <= #D tu_cnt << 1;
end

//key send to packet and key fifo
//sok
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      key_sok_ci <= #D 1'b0;
   else if(ip_cnt[2] && pre_dvld_key)
      key_sok_ci <= #D 1'b1;
   else
      key_sok_ci <= #D 1'b0;
end

//eok
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      key_eok_ci <= #D 1'b0;
   else if(~tu_flag && tu_cnt[2] && pre_dvld_key)
      key_eok_ci <= #D 1'b1;
   else if(tu_flag && tu_cnt[3] && pre_dvld_key)
      key_eok_ci <= #D 1'b1;
   else
      key_eok_ci <= #D 1'b0;
end

//key
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ip_tos <= #D 8'b0;
   else if(ip_cnt[0] && pre_dvld_key)
      ip_tos <= #D pre_dat_key[7:0];
end
reg   [31:0]  sip;
reg   [31:0]  dip;
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      sip <= #D 32'b0;
   else if(ip_cnt[4] && pre_dvld_key)
      sip <= #D {tmp_sd,pre_dat_key[31:16]};
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      dip <= #D 32'b0;
   else if(ip_cnt[5] && pre_dvld_key)
      dip <= #D {tmp_sd,pre_dat_key[31:16]};
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      tmp_sd <= #D 16'h0;
   else if(ip_cnt[3] && pre_dvld_key)
      tmp_sd <= #D pre_dat_key[15:0];
   else if(ip_cnt[4] && pre_dvld_key)
      tmp_sd <= #D pre_dat_key[15:0];
   else if(tu_cnt[0] && pre_dvld_key)
      tmp_sd <= #D pre_dat_key[15:0];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      key_key_ci <= #D 32'b0;
   else if(ip_cnt[2] && pre_dvld_key)
      key_key_ci <= #D 32'b0;
   else if(ip_cnt[4] && pre_dvld_key)
      key_key_ci <= #D {tmp_sd,pre_dat_key[31:16]};  //sip
   else if(ip_cnt[5] && pre_dvld_key)
      key_key_ci <= #D {tmp_sd,pre_dat_key[31:16]};  //dip
   else if(tu_cnt[1] && pre_dvld_key)
      key_key_ci <= #D {tmp_sd,pre_dat_key[31:16]};  //sport + dport
   else if(tu_flag && tu_cnt[3] && pre_dvld_key)
      key_key_ci <= #D 32'b0;
   else
      key_key_ci <= #D 32'b0;
end

//always @ (posedge sys_clk or negedge sys_rst_n)   //used for debug
//begin
//   if(!sys_rst_n)
//      key_key_ci <= #D 32'b0;
//   else if(tu_flag && tu_cnt[3] && pre_dvld_key)
//      key_key_ci <= #D {16'b1,16'd0};
//   else
//      key_key_ci <= #D 32'b0;
//end

//kvld
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      key_kvld_ci <= #D 1'b0;
   else if((ip_cnt[2] || ip_cnt[4] || ip_cnt[5] || tu_cnt[1] ||
            tu_flag && tu_cnt[3] || ~tu_flag && tu_cnt[2]) && pre_dvld_key)
      key_kvld_ci <= #D 1'b1;
   else
      key_kvld_ci <= #D 1'b0;
end

endmodule