len_cal.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

// find out the short packet and long packet
//-----------------------------------------------------------------------------
// Title      : header lenth caculate module
// Project    : 
//-----------------------------------------------------------------------------
// File       : len_cal.v
// Author     : 
// Date       : 07-10-21
//-----------------------------------------------------------------------------
// Description: 
//
//-------------------------------------------------------------------------------
 
`timescale 1ns/10ps

module len_cal(
sys_clk,
sys_rst_n,
rmv_sop_cal,
rmv_eop_cal,
rmv_vld_cal,
rmv_err_cal,
rmv_dat_cal,
rmv_mod_cal,
cal_afull_rmv,
cal_sop_fc,
cal_eop_fc,
cal_dat_fc,
cal_mod_fc,
cal_vld_fc, 
cal_spkt_fc, 
cal_lpkt_fc, 
cal_epkt_fc,  
fc_afull_cal,
conf_wr_cal,
conf_rd_cal,
conf_clr_cal,
conf_addr_cal,
conf_wdat_cal,
cal_rdat_conf
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/
parameter  D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

/*-------system I/F --------*/
input               sys_clk;
input               sys_rst_n;

//      hd_rmv Interface
input               rmv_sop_cal;
input               rmv_eop_cal;
input               rmv_vld_cal;
input               rmv_err_cal;
input     [31:0]    rmv_dat_cal;
input     [1:0]     rmv_mod_cal;
output              cal_afull_rmv;  

//      fc Interface
output              cal_sop_fc;
output              cal_eop_fc;
output    [31:0]    cal_dat_fc;
output    [1:0]     cal_mod_fc;
output              cal_vld_fc;
output              cal_spkt_fc;     //short packet
output              cal_lpkt_fc;     //long  packet
output              cal_epkt_fc;     //error packet
input               fc_afull_cal;

/*------------conf I/F------------*/
input               conf_wr_cal;
input               conf_rd_cal;
input               conf_clr_cal;
input     [3:0]     conf_addr_cal;
input     [15:0]    conf_wdat_cal;
output    [15:0]    cal_rdat_conf;
/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg       [15:0]    long_pkt_cnt;    
reg       [15:0]    short_pkt_cnt;  
reg                 cal_afull_rmv;  
reg                 cal_sop_fc;
reg                 cal_eop_fc;
reg       [31:0]    cal_dat_fc;
reg       [1:0]     cal_mod_fc;
reg                 cal_vld_fc;
reg                 cal_spkt_fc;     //short packet
reg                 cal_lpkt_fc;     //long  packet
reg                 cal_epkt_fc;     //error packet

reg                 f_sop;
reg                 f_eop;
reg                 f_vld;
reg                 f_err;
reg       [31:0]    f_dat;
reg       [1:0]     f_mod;
reg                 f2_sop;
reg                 f2_eop;
reg                 f2_vld;
reg                 f2_err;
reg       [31:0]    f2_dat;
reg       [1:0]     f2_mod;
reg       [2:0]     vld_bytes;
reg       [10:0]    pkt_len;
wire                short_pkt;
wire                long_pkt;
reg                 long_pkt_d;

reg      [10:0]    long_pkt_size;
reg      [10:0]    short_pkt_size;
reg                clr_lpkt_cnt;
reg                clr_spkt_cnt;

reg                conf_wr;
reg                conf_rd;
reg                conf_clr;
reg   [3:0]        conf_addr;
reg   [15:0]       conf_wdat;
reg   [15:0]       cal_rdat_conf;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/        

/*-------- pushback signal -----------*/
always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      cal_afull_rmv <= #D 0;
   else
      cal_afull_rmv <= #D fc_afull_cal;

/*----------- statistics ------------- */
       
//long packet counter
always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      long_pkt_cnt <= #D 16'b0;
   else if(clr_lpkt_cnt)
      long_pkt_cnt <= #D 16'b0;
   else if(cal_eop_fc && cal_vld_fc && cal_lpkt_fc) 
      long_pkt_cnt <= #D long_pkt_cnt + 1;

//short packet counter
always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      short_pkt_cnt <= #D 16'b0;
   else if(clr_spkt_cnt)
      short_pkt_cnt <= #D 16'b0;
   else if(cal_eop_fc && cal_vld_fc && cal_spkt_fc) 
      short_pkt_cnt <= #D short_pkt_cnt + 1;

/*------------ calculation -------------*/

//register inputs
always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
   begin
      f_sop <= #D 0;
      f_eop <= #D 0;
      f_vld <= #D 0;
      f_err <= #D 0;
      f_dat <= #D 32'b0;
      f_mod <= #D 2'b0;
      
      f2_sop <= #D 0;
      f2_eop <= #D 0;
      f2_vld <= #D 0;
      f2_err <= #D 0;
      f2_dat <= #D 32'b0;
      f2_mod <= #D 2'b0;
   end
   else
   begin
      f_sop <= #D rmv_sop_cal;
      f_eop <= #D rmv_eop_cal;
      f_vld <= #D rmv_vld_cal;
      f_err <= #D rmv_err_cal;
      f_dat <= #D rmv_dat_cal;
      f_mod <= #D rmv_mod_cal;
      
      f2_sop <= #D f_sop;
      f2_eop <= #D f_eop;
      f2_vld <= #D f_vld;
      f2_err <= #D f_err;
      f2_dat <= #D f_dat;
      f2_mod <= #D f_mod;
   end

always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      vld_bytes <= #D 3'b0;
   else if(rmv_eop_cal && rmv_vld_cal)
      case(rmv_mod_cal)
        2'b00:   vld_bytes <= #D 3'b100;
        2'b01:   vld_bytes <= #D 3'b011;
        2'b10:   vld_bytes <= #D 3'b010;
        2'b11:   vld_bytes <= #D 3'b001;
        default: vld_bytes <= #D 3'b0;
      endcase
    else if(rmv_vld_cal)
       vld_bytes <= #D 3'b100;
    else 
       vld_bytes <= #D 3'b0;

always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      pkt_len <= #D 11'b0;
   else if(f2_eop && f2_vld)
      pkt_len <= #D 11'b0;
   else if(long_pkt_d)
      pkt_len <= #D pkt_len;
   else if(f_vld)
      pkt_len <= #D pkt_len + vld_bytes;
      
assign short_pkt = pkt_len < short_pkt_size;
assign long_pkt  = pkt_len > long_pkt_size;      

always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
      long_pkt_d <= #D 0;
   else
      long_pkt_d <= #D long_pkt;

always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
   begin
      cal_sop_fc  <= #D 0;
      cal_dat_fc  <= #D 32'b0;
      cal_eop_fc  <= #D 0;
      cal_vld_fc  <= #D 0;
      cal_epkt_fc <= #D 0;
      cal_spkt_fc <= #D 0;
      cal_lpkt_fc <= #D 0;
   end
   else
   begin
      cal_sop_fc  <= #D f2_sop;
      cal_dat_fc  <= #D f2_dat;
      cal_eop_fc  <= #D f2_eop && f2_vld && ~long_pkt || long_pkt && ~long_pkt_d; 
      cal_vld_fc  <= #D f2_vld && ~long_pkt_d;
      cal_epkt_fc <= #D f2_err;
      cal_spkt_fc <= #D f2_eop && f2_vld && short_pkt;
      cal_lpkt_fc <= #D long_pkt && ~long_pkt_d;
   end


always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      cal_mod_fc <= #D 2'b0;
   else if(f2_eop && f2_vld && ~long_pkt)
      cal_mod_fc <= #D f2_mod;
   else if(long_pkt && ~long_pkt_d)
      case(long_pkt_size[1:0])
        2'b00:   cal_mod_fc <= #D 2'b00;
        2'b01:   cal_mod_fc <= #D 2'b11;
        2'b10:   cal_mod_fc <= #D 2'b10;
        2'b11:   cal_mod_fc <= #D 2'b01;
        default: cal_mod_fc <= #D 2'b00;
      endcase
   else
      cal_mod_fc <= #D 2'b00;
end

//register inputs
always @ (posedge sys_clk or negedge sys_rst_n)
   if(!sys_rst_n)
   begin
      conf_wr   <= #D 0;
      conf_rd   <= #D 0;
      conf_clr  <= #D 0;
      conf_addr <= #D 4'b0;
      conf_wdat <= #D 16'b0;
   end
   else
   begin
      conf_wr   <= #D conf_wr_cal;
      conf_rd   <= #D conf_rd_cal;
      conf_clr  <= #D conf_clr_cal;
      conf_addr <= #D conf_addr_cal;
      conf_wdat <= #D conf_wdat_cal;
   end

//address 0x  : short_pkt_size
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      short_pkt_size <= #D 11'd48;
   else if(conf_wr && conf_addr[3:0] == 4'h1)
      short_pkt_size <= #D conf_wdat[10:0];
end

//address 0x  : long_pkt_size
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      long_pkt_size <= #D 11'd1536;
   else if(conf_wr && conf_addr[3:0] == 4'h2)
      long_pkt_size <= #D conf_wdat[10:0];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      clr_spkt_cnt <= 1'b0;
   else
      clr_spkt_cnt <= #D conf_clr && conf_addr[3:0] == 4'd3;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      clr_lpkt_cnt <= 1'b0;
   else
      clr_lpkt_cnt <= #D conf_clr && conf_addr[3:0] == 4'd4;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     cal_rdat_conf <= #D 16'b0;
  else if(conf_rd)
  begin
    case(conf_addr)
    4'd0:    cal_rdat_conf <= #D 16'b0;
    4'd1:    cal_rdat_conf <= #D short_pkt_size;
    4'd2:    cal_rdat_conf <= #D long_pkt_size;
    4'd3:    cal_rdat_conf <= #D short_pkt_cnt;
    4'd4:    cal_rdat_conf <= #D long_pkt_cnt;
    default: cal_rdat_conf <= #D 16'b0;
    endcase
  end
end

endmodule