pci_top_bb.v

pci转local bus总线的应用

// Generated by PCI Compiler 4.0.0 [Altera, IP Toolbench v1.2.9 build44]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2007 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.

module pci_top (
	clk,
	rstn,
	idsel,
	l_adi,
	lt_rdyn,
	lt_abortn,
	lt_discn,
	lirqn,
	cben,
	framen,
	irdyn,
	intan,
	serrn,
	l_adro,
	l_dato,
	l_beno,
	l_cmdo,
	lt_framen,
	lt_ackn,
	lt_dxfrn,
	lt_tsr,
	cmd_reg,
	stat_reg,
	perrn,
	devseln,
	trdyn,
	stopn,
	ad,
	par);

	input		clk;
	input		rstn;
	input		idsel;
	input	[31:0]	l_adi;
	input		lt_rdyn;
	input		lt_abortn;
	input		lt_discn;
	input		lirqn;
	input	[3:0]	cben;
	input		framen;
	input		irdyn;
	output		intan;
	output		serrn;
	output	[31:0]	l_adro;
	output	[31:0]	l_dato;
	output	[3:0]	l_beno;
	output	[3:0]	l_cmdo;
	output		lt_framen;
	output		lt_ackn;
	output		lt_dxfrn;
	output	[11:0]	lt_tsr;
	output	[6:0]	cmd_reg;
	output	[6:0]	stat_reg;
	output		perrn;
	output		devseln;
	output		trdyn;
	output		stopn;
	inout	[31:0]	ad;
	inout		par;
endmodule