sub_tdm.fit.rpt

pci转local bus总线的应用

; parallel_interface:Parallel_interface|cpld_rd~130  ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|cpld_wr~181  ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|cpu_cs_n~132 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|cpu_oe_n~121 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|cpu_we_n~91  ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|dir~43       ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|rtc_cs_n~206 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|rtc_ds~73    ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
; parallel_interface:Parallel_interface|rtc_rw~72    ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                  ;                  ;
+----------------------------------------------------+---------+------------------+---------------------+-----------+------------------+------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/232/sub_tdm.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/232/sub_tdm.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 1,565 / 5,980 ( 26 % ) ;
;     -- Combinational with no register       ; 765                    ;
;     -- Register only                        ; 134                    ;
;     -- Combinational with a register        ; 666                    ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 643                    ;
;     -- 3 input functions                    ; 316                    ;
;     -- 2 input functions                    ; 312                    ;
;     -- 1 input functions                    ; 181                    ;
;     -- 0 input functions                    ; 113                    ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 1506                   ;
;     -- arithmetic mode                      ; 59                     ;
;     -- qfbk mode                            ; 200                    ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 351                    ;
;     -- asynchronous clear/load mode         ; 758                    ;
;                                             ;                        ;
; Total LABs                                  ; 179 / 598 ( 29 % )     ;
; Logic elements in carry chains              ; 66                     ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 180 / 185 ( 97 % )     ;
;     -- Clock pins                           ; 2 / 2 ( 100 % )        ;
; Global signals                              ; 7                      ;
; M4Ks                                        ; 0 / 20 ( 0 % )         ;
; Total memory bits                           ; 0 / 92,160 ( 0 % )     ;
; Total RAM block bits                        ; 0 / 92,160 ( 0 % )     ;
; Global clocks                               ; 7 / 8 ( 87 % )         ;
; Maximum fan-out node                        ; reset_n                ;
; Maximum fan-out                             ; 773                    ;
; Total fan-out                               ; 6865                   ;
; Average fan-out                             ; 3.93                   ;
+---------------------------------------------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LogicLock Region Resource Usage                                                                                                                                                          ;
+----------------------+--------+-------+--------+-------------+--------------+-------------+-------+--------------+--------------+-------------------+------------------+-----------------+
; LogicLock Region     ; Origin ; Width ; Height ; Logic Cells ; LC Registers ; Memory Bits ; Pins  ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ;
+----------------------+--------+-------+--------+-------------+--------------+-------------+-------+--------------+--------------+-------------------+------------------+-----------------+
; pci_t32:pci_t32_inst ; X5_Y1  ; 11    ; 7      ; 710 (710)   ; 292 (292)    ; 0 (0)       ; 0 (0) ; 0 (0)        ; 418 (418)    ; 60 (60)           ; 232 (232)        ; 2 (2)           ;
+----------------------+--------+-------+--------+-------------+--------------+-------------+-------+--------------+--------------+-------------------+------------------+-----------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+