sub_tdm.fit.rpt

pci转local bus总线的应用

Fitter report for sub_tdm
Mon Oct 30 12:04:18 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Netlist Optimizations
  6. Fitter Equations
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. LogicLock Region Resource Usage
 10. Input Pins
 11. Output Pins
 12. Bidir Pins
 13. I/O Bank Usage
 14. All Package Pins
 15. Output Pin Default Load For Reported TCO
 16. Fitter Resource Utilization by Entity
 17. Delay Chain Summary
 18. Pad To Core Delay Chain Fanout
 19. Control Signals
 20. Global & Other Fast Signals
 21. Non-Global High Fan-Out Signals
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-----------------------+--------------------------------------------------+
; Fitter Status         ; Successful - Mon Oct 30 12:04:18 2006            ;
; Quartus II Version    ; 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version ;
; Revision Name         ; sub_tdm                                          ;
; Top-level Entity Name ; top                                              ;
; Family                ; Cyclone                                          ;
; Device                ; EP1C6Q240C8                                      ;
; Timing Models         ; Final                                            ;
; Total logic elements  ; 1,565 / 5,980 ( 26 % )                           ;
; Total pins            ; 180 / 185 ( 97 % )                               ;
; Total virtual pins    ; 0                                                ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                               ;
; Total PLLs            ; 0 / 2 ( 0 % )                                    ;
+-----------------------+--------------------------------------------------+


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