sub_tdm.map.eqn

pci转local bus总线的应用

--C1_pi_addr[10] is parallel_interface:Parallel_interface|pi_addr[10]
--operation mode is normal

C1_pi_addr[10]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[12];
C1_pi_addr[10] = DFFEAS(C1_pi_addr[10]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[11] is parallel_interface:Parallel_interface|pi_addr[11]
--operation mode is normal

C1_pi_addr[11]_lut_out = M1_lt_adr[13];
C1_pi_addr[11] = DFFEAS(C1_pi_addr[11]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[12] is parallel_interface:Parallel_interface|pi_addr[12]
--operation mode is normal

C1_pi_addr[12]_lut_out = M1_lt_adr[14];
C1_pi_addr[12] = DFFEAS(C1_pi_addr[12]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[13] is parallel_interface:Parallel_interface|pi_addr[13]
--operation mode is normal

C1_pi_addr[13]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[15];
C1_pi_addr[13] = DFFEAS(C1_pi_addr[13]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[14] is parallel_interface:Parallel_interface|pi_addr[14]
--operation mode is normal

C1_pi_addr[14]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[16];
C1_pi_addr[14] = DFFEAS(C1_pi_addr[14]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[15] is parallel_interface:Parallel_interface|pi_addr[15]
--operation mode is normal

C1_pi_addr[15]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[17];
C1_pi_addr[15] = DFFEAS(C1_pi_addr[15]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[16] is parallel_interface:Parallel_interface|pi_addr[16]
--operation mode is normal

C1_pi_addr[16]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[18];
C1_pi_addr[16] = DFFEAS(C1_pi_addr[16]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[17] is parallel_interface:Parallel_interface|pi_addr[17]
--operation mode is normal

C1_pi_addr[17]_lut_out = M1_lt_adr[19];
C1_pi_addr[17] = DFFEAS(C1_pi_addr[17]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[18] is parallel_interface:Parallel_interface|pi_addr[18]
--operation mode is normal

C1_pi_addr[18]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[20];
C1_pi_addr[18] = DFFEAS(C1_pi_addr[18]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[19] is parallel_interface:Parallel_interface|pi_addr[19]
--operation mode is normal

C1_pi_addr[19]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[21];
C1_pi_addr[19] = DFFEAS(C1_pi_addr[19]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[20] is parallel_interface:Parallel_interface|pi_addr[20]
--operation mode is normal

C1_pi_addr[20]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[22];
C1_pi_addr[20] = DFFEAS(C1_pi_addr[20]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--C1_pi_addr[21] is parallel_interface:Parallel_interface|pi_addr[21]
--operation mode is normal

C1_pi_addr[21]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[23];
C1_pi_addr[21] = DFFEAS(C1_pi_addr[21]_lut_out, pci_clk, reset_n, , E1L054, , , , );


--M1_TS_IDLE_NOT is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|TS_IDLE_NOT
--operation mode is normal

M1_TS_IDLE_NOT = AMPP_FUNCTION(pci_clk, M1_TS_IDLE_d_lc, M1_TS_IDLE_d_lc1, P1L481, reset_n);


--P1_bar_hitR[3] is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|bar_hitR[3]
--operation mode is normal

P1_bar_hitR[3] = AMPP_FUNCTION(pci_clk, P1_bar_hit[3], P1_bar_hitR[3], M1_bar_hit_rst, reset_n);


--P1_bar_hitR[1] is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|bar_hitR[1]
--operation mode is normal

P1_bar_hitR[1] = AMPP_FUNCTION(pci_clk, P1_bar_hit[1], P1_bar_hitR[1], M1_bar_hit_rst, reset_n);


--J1_cben_ir_address[0] is pci_top:pci|pci_t32:pci_t32_inst|cben_ir_address[0]
--operation mode is normal

J1_cben_ir_address[0] = AMPP_FUNCTION(pci_clk, pci_c_be_n[0], reset_n, J1_cben_IR_ce_address);


--J1_cben_ir_address[3] is pci_top:pci|pci_t32:pci_t32_inst|cben_ir_address[3]
--operation mode is normal

J1_cben_ir_address[3] = AMPP_FUNCTION(pci_clk, pci_c_be_n[3], reset_n, J1_cben_IR_ce_address);


--J1_cben_ir_address[2] is pci_top:pci|pci_t32:pci_t32_inst|cben_ir_address[2]
--operation mode is normal

J1_cben_ir_address[2] = AMPP_FUNCTION(pci_clk, pci_c_be_n[2], reset_n, J1_cben_IR_ce_address);


--J1_cben_ir_address[1] is pci_top:pci|pci_t32:pci_t32_inst|cben_ir_address[1]
--operation mode is normal

J1_cben_ir_address[1] = AMPP_FUNCTION(pci_clk, pci_c_be_n[1], reset_n, J1_cben_IR_ce_address);


--C1L491 is parallel_interface:Parallel_interface|reduce_nor~1
--operation mode is normal

C1L491 = J1_cben_ir_address[0] # J1_cben_ir_address[3] # !J1_cben_ir_address[1] # !J1_cben_ir_address[2];


--C1L301 is parallel_interface:Parallel_interface|dir~42
--operation mode is normal

C1L301 = M1_TS_IDLE_NOT & !C1L491 & (P1_bar_hitR[3] # P1_bar_hitR[1]);


--C1_cpu_cs_n is parallel_interface:Parallel_interface|cpu_cs_n
--operation mode is normal

C1_cpu_cs_n_lut_out = !C1L1 & !C1L3 & (C1_cstate.IDLE # !C1L5);
C1_cpu_cs_n = DFFEAS(C1_cpu_cs_n_lut_out, pci_clk, reset_n, , , , , , );


--C1_cpu_oe_n is parallel_interface:Parallel_interface|cpu_oe_n
--operation mode is normal

C1_cpu_oe_n_lut_out = !C1L1 & !C1L6 & (!C1L9 # !C1L8);
C1_cpu_oe_n = DFFEAS(C1_cpu_oe_n_lut_out, pci_clk, reset_n, , , , , , );


--C1_cpu_we_n is parallel_interface:Parallel_interface|cpu_we_n
--operation mode is normal

C1_cpu_we_n_lut_out = !C1_cstate.WRITE_ZAR_3 & !C1L01 & (C1_cstate.IDLE # !C1L21);
C1_cpu_we_n = DFFEAS(C1_cpu_we_n_lut_out, pci_clk, reset_n, , , , , , );


--C1_cpu_ts_ale is parallel_interface:Parallel_interface|cpu_ts_ale
--operation mode is normal

C1_cpu_ts_ale_lut_out = C1L31 # C1L4 & C1L41 # !C1L51;
C1_cpu_ts_ale = DFFEAS(C1_cpu_ts_ale_lut_out, pci_clk, reset_n, , , , , , );


--pci_clk is pci_clk
pci_clk = INPUT();


--clk_25M is clk_25M
clk_25M = INPUT();


--E1_led_reg[2] is fpga_misc:misc|led_reg[2]
--operation mode is normal

E1_led_reg[2]_lut_out = !J1_low_ad_IR_data[2];
E1_led_reg[2] = DFFEAS(E1_led_reg[2]_lut_out, pci_clk, reset_n, , E1L403, , , , );


--E1_led_reg[1] is fpga_misc:misc|led_reg[1]
--operation mode is normal

E1_led_reg[1]_lut_out = !J1_low_ad_IR_data[1];
E1_led_reg[1] = DFFEAS(E1_led_reg[1]_lut_out, pci_clk, reset_n, , E1L403, , , , );


--E1_led_reg[0] is fpga_misc:misc|led_reg[0]
--operation mode is normal

E1_led_reg[0]_lut_out = !J1_low_ad_IR_data[0];
E1_led_reg[0] = DFFEAS(E1_led_reg[0]_lut_out, pci_clk, reset_n, , E1L403, , , , );


--B1L92 is INT_LED:INT_LED|run_led~8
--operation mode is normal

B1L92 = E1_led_reg[0] & D1_count[22] # !E1_led_reg[0] & (D1_count[24]);


--bcm5248_int[1] is bcm5248_int[1]
bcm5248_int[1] = INPUT();


--E1_int_mask[2] is fpga_misc:misc|int_mask[2]
--operation mode is normal

E1_int_mask[2]_lut_out = !J1_low_ad_IR_data[2];
E1_int_mask[2] = DFFEAS(E1_int_mask[2]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--E1_int_mask[8] is fpga_misc:misc|int_mask[8]
--operation mode is normal

E1_int_mask[8]_lut_out = !J1_low_ad_IR_data[8];
E1_int_mask[8] = DFFEAS(E1_int_mask[8]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--bcm5464_int_n[3] is bcm5464_int_n[3]
bcm5464_int_n[3] = INPUT();


--B1L71 is INT_LED:INT_LED|fpga_int~51
--operation mode is normal

B1L71 = bcm5248_int[1] & (!bcm5464_int_n[3] # !E1_int_mask[8]) # !bcm5248_int[1] & !E1_int_mask[2] & (!bcm5464_int_n[3] # !E1_int_mask[8]);


--bcm5248_int[0] is bcm5248_int[0]
bcm5248_int[0] = INPUT();


--E1_int_mask[1] is fpga_misc:misc|int_mask[1]
--operation mode is normal

E1_int_mask[1]_lut_out = !J1_low_ad_IR_data[1];
E1_int_mask[1] = DFFEAS(E1_int_mask[1]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--B1_bcm5248_int0 is INT_LED:INT_LED|bcm5248_int0
--operation mode is normal

B1_bcm5248_int0 = !bcm5248_int[0] & (E1_int_mask[1]);


--E1_int_mask[6] is fpga_misc:misc|int_mask[6]
--operation mode is normal

E1_int_mask[6]_lut_out = !J1_low_ad_IR_data[6];
E1_int_mask[6] = DFFEAS(E1_int_mask[6]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--bcm5464_int_n[1] is bcm5464_int_n[1]
bcm5464_int_n[1] = INPUT();


--B1_bcm5464_int1 is INT_LED:INT_LED|bcm5464_int1
--operation mode is normal

B1_bcm5464_int1 = E1_int_mask[6] & bcm5464_int_n[1];


--bcm5248_int[3] is bcm5248_int[3]
bcm5248_int[3] = INPUT();


--E1_int_mask[4] is fpga_misc:misc|int_mask[4]
--operation mode is normal

E1_int_mask[4]_lut_out = !J1_low_ad_IR_data[4];
E1_int_mask[4] = DFFEAS(E1_int_mask[4]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--B1_bcm5248_int3 is INT_LED:INT_LED|bcm5248_int3
--operation mode is normal

B1_bcm5248_int3 = !bcm5248_int[3] & (E1_int_mask[4]);


--E1_int_mask[5] is fpga_misc:misc|int_mask[5]
--operation mode is normal

E1_int_mask[5]_lut_out = !J1_low_ad_IR_data[5];
E1_int_mask[5] = DFFEAS(E1_int_mask[5]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--bcm5464_int_n[0] is bcm5464_int_n[0]
bcm5464_int_n[0] = INPUT();


--B1_bcm5464_int0 is INT_LED:INT_LED|bcm5464_int0
--operation mode is normal

B1_bcm5464_int0 = E1_int_mask[5] & bcm5464_int_n[0];


--E1_int_mask[7] is fpga_misc:misc|int_mask[7]
--operation mode is normal

E1_int_mask[7]_lut_out = !J1_low_ad_IR_data[7];
E1_int_mask[7] = DFFEAS(E1_int_mask[7]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--bcm5464_int_n[2] is bcm5464_int_n[2]
bcm5464_int_n[2] = INPUT();


--B1_bcm5464_int2 is INT_LED:INT_LED|bcm5464_int2
--operation mode is normal

B1_bcm5464_int2 = E1_int_mask[7] & bcm5464_int_n[2];


--bcm5248_int[2] is bcm5248_int[2]
bcm5248_int[2] = INPUT();


--E1_int_mask[3] is fpga_misc:misc|int_mask[3]
--operation mode is normal

E1_int_mask[3]_lut_out = !J1_low_ad_IR_data[3];
E1_int_mask[3] = DFFEAS(E1_int_mask[3]_lut_out, pci_clk, reset_n, , E1L482, , , , );


--B1_bcm5248_int2 is INT_LED:INT_LED|bcm5248_int2
--operation mode is normal

B1_bcm5248_int2 = !bcm5248_int[2] & (E1_int_mask[3]);


--B1L81 is INT_LED:INT_LED|fpga_int~52
--operation mode is normal

B1L81 = !B1_bcm5248_int3 & !B1_bcm5464_int0 & !B1_bcm5464_int2 & !B1_bcm5248_int2;


--B1L91 is INT_LED:INT_LED|fpga_int~53
--operation mode is normal

B1L91 = B1L71 & !B1_bcm5248_int0 & !B1_bcm5464_int1 & B1L81;


--C1_cpld_cs is parallel_interface:Parallel_interface|cpld_cs
--operation mode is normal

C1_cpld_cs_lut_out = !C1L91 & !C1L32 & (C1L37 # !C1L42);
C1_cpld_cs = DFFEAS(C1_cpld_cs_lut_out, pci_clk, reset_n, , , , , , );


--C1_cpld_wr is parallel_interface:Parallel_interface|cpld_wr
--operation mode is normal

C1_cpld_wr_lut_out = !C1L52 & C1L72 & (C1_cstate.IDLE # !C1L62);
C1_cpld_wr = DFFEAS(C1_cpld_wr_lut_out, pci_clk, reset_n, , , , , , );


--C1_cpld_rd is parallel_interface:Parallel_interface|cpld_rd
--operation mode is normal

C1_cpld_rd_lut_out = !C1L82 & C1L72 & (C1_cpld_rd # C1L81);
C1_cpld_rd = DFFEAS(C1_cpld_rd_lut_out, pci_clk, reset_n, , , , , , );


--C1_rtc_cs_n is parallel_interface:Parallel_interface|rtc_cs_n
--operation mode is normal

C1_rtc_cs_n_lut_out = !C1L402 & C1_rtc_cs_n # !C1L13 # !C1L03;
C1_rtc_cs_n = DFFEAS(C1_rtc_cs_n_lut_out, pci_clk, reset_n, , , , , , );


--C1_rtc_as is parallel_interface:Parallel_interface|rtc_as
--operation mode is normal

C1_rtc_as_lut_out = C1L23 # C1_rtc_as & (C1L33 # !C1L402);
C1_rtc_as = DFFEAS(C1_rtc_as_lut_out, pci_clk, reset_n, , , , , , );


--C1_rtc_rw is parallel_interface:Parallel_interface|rtc_rw
--operation mode is normal

C1_rtc_rw_lut_out = C1_cstate.RTC_WR & (C1_rtc_rw $ C1L43) # !C1_cstate.RTC_WR & C1_cstate.IDLE & C1_rtc_rw;
C1_rtc_rw = DFFEAS(C1_rtc_rw_lut_out, pci_clk, reset_n, , , , , , );


--C1_rtc_ds is parallel_interface:Parallel_interface|rtc_ds
--operation mode is normal

C1_rtc_ds_lut_out = !C1L53 & (C1_cstate.RTC_RD & !C1L332 # !C1_cstate.RTC_RD & (C1_cstate.IDLE));
C1_rtc_ds = DFFEAS(C1_rtc_ds_lut_out, pci_clk, reset_n, , , , , , );


--E1_g_status_reg[0] is fpga_misc:misc|g_status_reg[0]
--operation mode is normal

E1_g_status_reg[0]_lut_out = !J1_low_ad_IR_data[0];
E1_g_status_reg[0] = DFFEAS(E1_g_status_reg[0]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[1] is fpga_misc:misc|g_status_reg[1]
--operation mode is normal

E1_g_status_reg[1]_lut_out = !J1_low_ad_IR_data[1];
E1_g_status_reg[1] = DFFEAS(E1_g_status_reg[1]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[2] is fpga_misc:misc|g_status_reg[2]
--operation mode is normal

E1_g_status_reg[2]_lut_out = !J1_low_ad_IR_data[2];
E1_g_status_reg[2] = DFFEAS(E1_g_status_reg[2]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[3] is fpga_misc:misc|g_status_reg[3]
--operation mode is normal

E1_g_status_reg[3]_lut_out = !J1_low_ad_IR_data[3];
E1_g_status_reg[3] = DFFEAS(E1_g_status_reg[3]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[4] is fpga_misc:misc|g_status_reg[4]
--operation mode is normal

E1_g_status_reg[4]_lut_out = !J1_low_ad_IR_data[4];
E1_g_status_reg[4] = DFFEAS(E1_g_status_reg[4]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[5] is fpga_misc:misc|g_status_reg[5]
--operation mode is normal

E1_g_status_reg[5]_lut_out = !J1_low_ad_IR_data[5];
E1_g_status_reg[5] = DFFEAS(E1_g_status_reg[5]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[6] is fpga_misc:misc|g_status_reg[6]
--operation mode is normal

E1_g_status_reg[6]_lut_out = !J1_low_ad_IR_data[6];
E1_g_status_reg[6] = DFFEAS(E1_g_status_reg[6]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_g_status_reg[7] is fpga_misc:misc|g_status_reg[7]
--operation mode is normal

E1_g_status_reg[7]_lut_out = !J1_low_ad_IR_data[7];
E1_g_status_reg[7] = DFFEAS(E1_g_status_reg[7]_lut_out, pci_clk, reset_n, , E1L552, , , , );


--E1_f_status_reg[0] is fpga_misc:misc|f_status_reg[0]
--operation mode is normal

E1_f_status_reg[0]_lut_out = !J1_low_ad_IR_data[0];
E1_f_status_reg[0] = DFFEAS(E1_f_status_reg[0]_lut_out, pci_clk,