📄 fpga_misc.v
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// wdval <= 7'h5;
// wdo_d <= 1'b1;
ot_thr <= 8'h20;
//For Roma ot_thr >= 0xa
resetflag <= 1'b1;
cstate <= IDLE;
end
else
begin
case(cstate)
IDLE:
begin
ready_n <= 1'b1;
dog_clear <= 1'b1;
// i2c_cpld_ini <= 1'b0;
int_clear <=16'hffff;
IIC_ACCESS_INIT <= 1'b0;
SFPIIC_ACCESS_INIT <= 1'b0;
/* i2c2_ini <= 1'b0;
i2c3_ini <= 1'b0;
i2c4_ini <= 1'b0; */
// uart_tx_start <= 1'b0;
// uart_data_rd <= 1'b0;
if(resetflag)
begin
resetflag <= 1'b0;
end
/* wdi <= 1'b0;
wdo_d <= wdo;
if(!wdo_d && wdo)
begin
wden <= 1'b0;
wdf <= 1'b1;
end */
if(!cs_n && !lt_framen)
cstate <= (wr_n) ? READ : WRITE;
else
cstate <= IDLE;
end
READ:
begin
// dog_clear <= 1'b1;
int_clear <=16'hffff;
IIC_ACCESS_INIT <= 1'b0;
SFPIIC_ACCESS_INIT <= 1'b0;
cstate <= (cs_n && lt_framen) ? IDLE : READ;
ready_n <= 1'b0;
case(addr_in)
10'h000: data_out[31:0] <= test_reg0;
10'h001: data_out[31:0] <= 32'h80081158;
10'h002: data_out[31:0] <= {26'h0,reset_reg[5:0]};
10'h003: data_out[31:0] <= 32'b0;//{14'h3fff , 2'b1, int_in_n};
10'h004: data_out[31:0] <= {16'b0,int_mask};
10'h005: data_out[31:0] <= {16'b0,int_state};
10'h006: data_out[31:0] <= 32'b0;
// 10'h007: data_out[31:0] <= 32'b0;//{16'b0 , wdf , wden , wdi , 6'b0 , wdval};
10'h008: data_out[31:0] <= {27'h0 , led_reg};
10'h009: data_out[31:0] <= 32'b0;//{15'b0 , sys_alerm};
10'h00a: data_out[31:0] <= 32'b0;//{15'b0 , sys_role};
10'h00b: data_out[31:0] <= {24'h0,dog_cnt};
10'h00c: data_out[31:0] <= {24'h0,dog_value};
// 10'h00d: data_out[31:0] <= 32'b0;//{26'b0,IIC_ACCESS_ERR,IIC_ACCESS_BUSY,IIC_ADDR,IIC_W_R};
10'h00e: data_out[31:0] <= 32'b0;//{6'b0 , i2c4_no_ack , i2c4_ready , i2c4_data_out , i2c4_sa , i2c4_rw , i2c4_ra};
10'h01d: data_out[31:0] <= {24'b0 , ot_thr};
10'h01e: data_out[31:0] <= err_cnt;
10'h01f: data_out[31:0] <= test_reg1;
10'h020: data_out[31:0] <= 32'b0;//{31'b0 , rst_out_reg_n[0]};
10'h021: data_out[31:0] <= {24'b0 , g_status_reg[7:0]};
10'h022: data_out[31:0] <= {24'b0 , f_status_reg[7:0]};
10'h023: data_out[31:0] <= {28'b0 , lc1_mod_type_reg};
10'h024: data_out[31:0] <= {28'b0 , lc2_mod_type_reg};
10'h025: data_out[31:0] <= {30'b0 , present_n_reg};
10'h026: data_out[31:0] <= {16'b0 , SFPIIC_DATA_IN};
10'h027: data_out[31:0] <= {24'b0 , SFPIIC_DATA_OUT};
10'h028: data_out[31:0] <= {18'b0 , SFPSLAVE_ADDR,SFP_ADDRESS,1'b0,SFPIIC_ACCESS_ERR,SFPIIC_ACCESS_BUSY,SFPIIC_W_R};
10'h029: data_out[31:0] <= {16'h0,IIC_DATA_IN};
10'h02a: data_out[31:0] <= {24'h0,IIC_DATA_OUT};
10'h02b: data_out[31:0] <= {29'h0,IIC_ACCESS_ERR,IIC_ACCESS_BUSY,IIC_W_R};
/* 10'h02c: data_out[31:0] <= {31'b0 , rst_out_reg_n[12]};
10'h02d: data_out[31:0] <= {31'b0 , rst_out_reg_n[13]};
10'h02e: data_out[31:0] <= {31'b0 , rst_out_reg_n[14]};
10'h02f: data_out[31:0] <= {31'b0 , rst_out_reg_n[15]};
*/
10'h031: data_out[31:0] <= 32'b0;
// begin
// data_out[31:0] <= {7'b0 , uart_rx_error , uart_data_out , 7'b0 , uart_tx_rdy , uart_data_in};
// uart_data_rd <= 1'b1;
// end
10'h032: data_out[31:0] <= 32'b0;//{31'b0 , bp_fan_alerm};
10'h033: data_out[31:0] <= 32'b0;//{28'b0 , bp_res[3:0]};
10'h034: data_out[31:0] <= 32'b0;//{28'b0 , ga[3:0]};
10'h035: data_out[31:0] <= 32'b0;//{30'b0 , sys[2:1]};
10'h036: data_out[31:0] <= 32'b0;//{30'b0 , slave[2:1]};
10'h100: data_out[31:0] <= 32'b0;//{31'b0 , pi_drdy_n};
default: data_out[31:0] <= 32'h0;
endcase
end
WRITE:
begin
cstate <= (cs_n && lt_framen) ? IDLE : WRITE;
ready_n <= 1'b0;
if(!lt_dxfrn && !lt_ackn)
begin
case(addr_in)
10'h000: test_reg0 <= data_in[31:0];
// 10'h001: <= data_in[31:0];
10'h002: reset_reg <= data_in[5:0];
// 10'h003: <= data_in[31:0];
10'h004: int_mask <= data_in[15:0];
10'h005: int_clear <= data_in[15:0];
// 10'h006: f_status_reg <= data_in[7:0];
10'h007: reset_reg[6] <= 1'b0;
10'h008: led_reg <= data_in[4:0];
// 10'h009: led_reg <= data_in[4:0];
// 10'h00a: sys_role <= data_in[0];*/
10'h00c: dog_value <= data_in[7:0];
10'h00d: dog_clear <= 1'b0;
/* begin
i2c3_ini <= 1'b1;
i2c3_data_in <= data_in[23:16];
i2c3_sa <= data_in[15:9];
i2c3_rw <= data_in[8];
i2c3_ra <= data_in[7:0];
end
10'h00e:
begin
i2c4_ini <= 1'b1;
i2c4_data_in <= data_in[23:16];
i2c4_sa <= data_in[15:9];
i2c4_rw <= data_in[8];
i2c4_ra <= data_in[7:0];
end */
10'h01d: ot_thr <= data_in[7:0];
// 10'h01e: <= data_in[31:0];
10'h01f: test_reg1 <= data_in[31:0];
// 10'h020: rst_out_reg_n[0] <= data_in[0];
10'h021: g_status_reg[7:0] <= data_in[7:0];
10'h022: f_status_reg[7:0] <= data_in[7:0];
/* 10'h023: rst_out_reg_n[3] <= data_in[0];
10'h024: rst_out_reg_n[4] <= data_in[0];
10'h025: rst_out_reg_n[5] <= data_in[0];*/
10'h026: SFPIIC_DATA_IN <= data_in[15:0];
// 10'h027: rst_out_reg_n[7] <= data_in[0];
10'h028:
begin
SFPIIC_W_R <= data_in[0];
SFP_ADDRESS <= data_in[6:4];
SFPSLAVE_ADDR <= data_in[13:7];
SFPIIC_ACCESS_INIT <= 1'b1;
end
10'h029: IIC_DATA_IN <= data_in[15:0];
// 10'h02a: rst_out_reg_n[10] <= data_in[0];
10'h02b:
begin
IIC_W_R <= data_in[0];
// IIC_ADDR <= data_in[3:1];
IIC_ACCESS_INIT <= 1'b1;
end
/* 10'h02c: rst_out_reg_n[12] <= data_in[0];
10'h02d: rst_out_reg_n[13] <= data_in[0];
10'h02e: rst_out_reg_n[14] <= data_in[0];
10'h02f: rst_out_reg_n[15] <= data_in[0];
*/
// 10'h031:
/* begin
uart_tx_start <= 1'b1;
uart_data_in <= data_in[7:0];
end
*/
default: ;
endcase
end
end
default: cstate <= IDLE;
endcase
end
end
/***Reset**********************************************************************/
/*reset reset (
// .rst_in_n ( rst_in_n ),
.rst_from_cpu_n ( rst_from_cpu_n),
.reset_n ( reset_n ),
.rst_out_n ( rst_out_n ),
.rst_out_reg_n ( rst_out_reg_n ));
// .wdo ( wdo ));
/*
RST_N0 -- N/A
RST_N1 -- NPU (NP-1C)
RST_N2 -- SerDes (VSC7280)
RST_N3 -- Switch (KS8995)
RST_N4 -- RTC
RST_N5 -- N/A
RST_N6 -- MAC (VSC7324)
RST_N7 -- PHY0 (VSC8224)
RST_N8 -- PHY1 (VSC8224)
RST_N9 -- PHY2 (VSC8224)
RST_N10-- PHY3 (VSC8224)
RST_N11-- PHY4 (VSC8224)
RST_N12-- PHY5 (VSC8224)
RST_N13-- N/A
RST_N14-- N/A
RST_N15-- N/A
*/
/***Interrupt******************************************************************/
/*interrupt interrupt (
.int_out_n ( int_out_n ),
.int_in_n ( {14'h3fff , 2'b1, int_in_n} ),
.int_mask ( int_mask ));*/
/*
INT_N0 -- SerDes (VSC7280)
INT_N1 -- N/A
INT_N2 -- N/A
INT_N3 -- RTC
INT_N4 -- PHY0 (VSC8224)
INT_N5 -- PHY1 (VSC8224)
INT_N6 -- PHY2 (VSC8224)
INT_N7 -- PHY3 (VSC8224)
INT_N8 -- PHY4 (VSC8224)
INT_N9 -- PHY5 (VSC8224)
INT_N10-- N/A
INT_N11-- N/A
INT_N12-- N/A
INT_N13-- N/A
INT_N14-- N/A
INT_N15-- N/A
INT_N16-- bp_fan_int_n
INT_N17-- uart_int_n
*/
/***IIC***如有必要，可以所有IIC接口复用一个模块，以减少资源消耗****************/
/***IIC to Cy22394*************************************************************/
/*
[31:26] reserved
[25] i2c_no_ack
[24] i2c_ready
[23:16] i2c_data
[15:9] i2c_slave_address
[8] i2c_rw
[7:0] i2c_register_address
操作方法：
1、每次读写操作前先确认i2c_ready＝1
2、读操作先写地址，
200us后读数，
确认i2c_no_ack＝0 则读数据有效
3、写操作直接填入地址数据
200us后读数，
确认i2c_no_ack＝0 则写数据成功
4、每个I2C操作周期约为200us
注意：接收到ini信号后要过约4us操作才真正开始（Ready=0）
因而不能在发起操作后马上读取Ready来判断操作是否完成，此时操作还没开始。
造成的后果是读操作时取得的数据是上次操作留下的。
*/
IIC_SFP IIC_SFP(
.CLK33M(clock),
.RESET_N(reset_n),
.IIC_DATA_IN(SFPIIC_DATA_IN),
.IIC_DATA_OUT(SFPIIC_DATA_OUT),
.IIC_ACCESS_INIT(SFPIIC_ACCESS_INIT),
.IIC_W_R(SFPIIC_W_R),
.SLAVE_ADDR(SFPSLAVE_ADDR),
.IIC_ACCESS_BUSY(SFPIIC_ACCESS_BUSY),
.IIC_ACCESS_ERR(SFPIIC_ACCESS_ERR),
.IIC_SCL(SFPIIC_SCL),
.IIC_SDA(SFPIIC_SDA),
.TRI_IIC_SDA(TRI_SFPIIC_SDA),
);
IIC_RS232 IIC_RS232(
.CLK33M ( clock ),
.RESET_N ( reset_n ),
.IIC_DATA_IN (IIC_DATA_IN),
.IIC_DATA_OUT (IIC_DATA_OUT),
.IIC_ACCESS_INIT (IIC_ACCESS_INIT),
.IIC_W_R (IIC_W_R),
.IIC_ACCESS_BUSY(IIC_ACCESS_BUSY),
.IIC_ACCESS_ERR(IIC_ACCESS_ERR),
.IIC_SCL(IIC_SCL),
.IIC_SDA(IIC_SDA)
);
/*i2c i2c_cy2 (
.clock ( clock ),
.reset_n ( reset_n ),
.scl ( i2c_scl ),
.sda ( i2c_sda ),
.no_ack ( i2c_cpld_no_ack ),
.ready ( i2c_cpld_ready ),
.data_in ( i2c_cpld_data_in ),
.data_out ( i2c_cpld_data_out ),
.sa ( i2c_cpld_sa ),
.rw ( i2c_cpld_rw ),
.ra ( i2c_cpld_ra ),
.ini ( i2c_cpld_ini ));
*/
/*
i2c i2c_cy2 (
.clock ( clock ),
.reset_n ( reset_n ),
.scl ( i2c_cy2_scl ),
.sda ( i2c_cy2_sda ),
.no_ack ( i2c2_no_ack ),
.ready ( i2c2_ready ),
.data_in ( i2c2_data_in ),
.data_out ( i2c2_data_out ),
.sa ( i2c2_sa ),
.rw ( i2c2_rw ),
.ra ( i2c2_ra ),
.ini ( i2c2_ini ));
/***I2C to EEPROM**************************************************************/
/*i2c i2c_eeprom (
.clock ( clock ),
.reset_n ( reset_n ),
.scl ( eeprom_i2c_scl ),
.sda ( eeprom_i2c_sda ),
.no_ack ( i2c3_no_ack ),
.ready ( i2c3_ready ),
.data_in ( i2c3_data_in ),
.data_out ( i2c3_data_out ),
.sa ( i2c3_sa ),
.rw ( i2c3_rw ),
.ra ( i2c3_ra ),
.ini ( i2c3_ini ));
/***I2C to backplane***********************************************************/
/*i2c i2c_backplane (
.clock ( clock ),
.reset_n ( reset_n ),
.scl ( bp_fan_scl ),
.sda ( bp_fan_sda ),
.no_ack ( i2c4_no_ack ),
.ready ( i2c4_ready ),
.data_in ( i2c4_data_in ),
.data_out ( i2c4_data_out ),
.sa ( i2c4_sa ),
.rw ( i2c4_rw ),
.ra ( i2c4_ra ),
.ini ( i2c4_ini ));
/***UART to Backplane**********************************************************/
/*v_uart v_uart (
.clock ( clock ),
.reset_n ( reset_n ),
.rxd ( uart_rxd ),
.txd ( uart_txd ),
.data_in ( uart_data_in ),
.data_out ( uart_data_out ),
.tx_ready ( uart_tx_rdy ),
.framing_error ( uart_rx_error ),
.data_ready ( uart_data_rdy ),
.data_rd ( uart_data_rd ),
.tx_start ( uart_tx_start ));*/
/***Watchdog*******************************************************************/
/*watchdog watchdog (
.clk ( clock ),
.rst_n ( reset_n ),
.wdval ( wdval ),
.wden ( wden ),
.wdi ( wdi ),
.wdo ( wdo ));*/
/******************************************************************************/
endmodule
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