rayleigh1.mdl

瑞利信道仿真

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    Block {
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      Multiplication	      "Element-wise(.*)"
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    Block {
      BlockType		      Reference
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    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Configuration Parameters: Optimiza"
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      LogicDataType	      "uint(8)"
      ZeroCross		      on
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    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
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    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
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    Block {
      BlockType		      TriggerPort
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    VerticalAlignment	    "middle"
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    Name		    "rayleigh1"
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    Open		    on
    ModelBrowserVisibility  off
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    PaperUnits		    "centimeters"
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      Position		      [255, 134, 335, 176]
      SourceBlock	      "commchan2/AWGN\nChannel"
      SourceType	      "AWGN Channel"
      ShowPortLabels	      on
      seed		      "67"
      noiseMode		      "Signal to noise ratio  (SNR)"
      EbNodB		      "30"
      EsNodB		      "10"
      SNRdB		      "SNR(i)"
      bitsPerSym	      "1"
      Ps		      "1"
      Tsym		      "0.003/4"
      variance		      "1"
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      BlockType		      Reference
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      Position		      [680, 126, 755, 174]
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      BlockType		      Reference
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      Position		      [470, 60, 525, 100]
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      SourceType	      "Delay"
      dly_unit		      "Samples"
      delay		      "4"
      ic_detail		      off
      dif_ic_for_ch	      off
      dif_ic_for_dly	      off
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      reset_popup	      "None"
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      BlockType		      Product
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      Position		      [605, 132, 635, 163]
      Inputs		      "*/"
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      OutScaling	      "2^-10"
      RndMeth		      "Floor"
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      Position		      [425, 138, 460, 172]
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      SourceType	      "Downsample"
      N			      "4"
      phase		      "0"
      ic		      "0"
      smode		      "Allow multirate"
      fmode		      "Maintain input frame rate"
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    Block {
      BlockType		      Reference
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      Position		      [560, 312, 635, 363]
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      SourceType	      "Error Rate Calculation"
      N			      "3"
      st_delay		      "0"
      cp_mode		      "Entire frame"
      subframe		      "[]"
      PMode		      "Workspace"
      WsName		      "ErrorVec"
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      stop		      off
      numErr		      "100"
      maxBits		      "1e6"
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    Block {
      BlockType		      Reference
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      Position		      [500, 129, 565, 181]
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      DialogControllerArgs    "DataTag0"
      SourceBlock	      "dspmlti4/FIR\nInterpolation"
      SourceType	      "FIR Interpolation"
      h			      "fir1(4,0.2)"
      L			      "4"
      framing		      "Maintain input frame rate"
      outputBufInitCond	      "0"
      additionalParams	      off
      allowOverrides	      on
      firstCoeffMode	      "Same word length as input"
      firstCoeffWordLength    "16"
      firstCoeffFracLength    "15"
      outputMode	      "Same as accumulator"
      outputWordLength	      "16"
      outputFracLength	      "15"
      accumMode		      "Inherit via internal rule"
      accumWordLength	      "32"
      accumFracLength	      "30"
      prodOutputMode	      "Inherit via internal rule"
      prodOutputWordLength    "32"
      prodOutputFracLength    "30"
      roundingMode	      "Floor"
      overflowMode	      off
      LockScale		      off
    }
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      BlockType		      Reference
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      Position		      [125, 133, 205, 177]
      SourceBlock	      "commchan2/Multipath Rayleigh\nFading Channel"
      SourceType	      "Multipath Rayleigh Fading Channel"
      ShowPortLabels	      on
      Fd		      "100"
      simTs		      "0.75e-5"
      delayVec		      "[0 ]"
      gainVecdB		      "[1.3]"
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      SourceType	      "Multiport Selector"
      rowsOrCols	      "Rows"
      idxCellArray	      "{ [2:4] }"
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      RTWSystemCode	      "Auto"
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	  Ports			  [1, 1]
	  Position		  [160, 91, 235, 139]
	  SourceBlock		  "commdigbbndpm2/BPSK\nModulator\nBaseband"
	  SourceType		  "BPSK Modulator Baseband"
	  ShowPortLabels	  on
	  Ph			  "0"
	  numSamp		  "1"
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	Block {
	  BlockType		  Reference
	  Name			  "Bernoulli Binary\nGenerator"
	  Ports			  [0, 1]
	  Position		  [25, 93, 105, 137]
	  FontName		  "Arial"
	  SourceBlock		  "commrandsrc2/Bernoulli Binary\nGenerator"
	  SourceType		  "Bernoulli Binary Generator"
	  ShowPortLabels	  on
	  P			  "0.5"
	  seed			  "61"
	  Ts			  "1e-5"
	  frameBased		  on
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	  orient		  off
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	Block {
	  BlockType		  Constant
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	  Position		  [120, 25, 150, 55]
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	Block {
	  BlockType		  Reference
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	  Ports			  [2, 1]
	  Position		  [280, 79, 335, 121]
	  SourceBlock		  "simulink/Math\nOperations/Matrix\nConcatena"
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	  SourceType		  "Matrix Concatenation"
	  numInports		  "2"
	  catMethod		  "Vertical"
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	  BusOutputAsStruct	  off
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      Points		      [240, 0; 0, 140]
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