tr_dff2.vhd

来自「提供了一个硬判决的viterbi译码器（2」· VHDL 代码 · 共 24 行

--tr_dff2.vhd  
--v0.1

library ieee;
use ieee.std_logic_1164.all;

entity tr_dff2 is 
	port(
		clk: in std_logic;
		in_outp: in std_logic_vector(1 downto 0);
		out_outp: out std_logic_vector(1 downto 0)
		);
end tr_dff2;

architecture a of tr_dff2 is
begin
process(clk,in_outp)
begin
	if rising_edge(clk) then
		out_outp<=in_outp;
	end if;
end process;
end a;