acs_1.hier_info

提供了一个硬判决的viterbi译码器（2

|ACS_1
clk => om_1[0]~reg0.CLK
clk => om_1[1]~reg0.CLK
clk => om_1[2]~reg0.CLK
clk => om_1[3]~reg0.CLK
clk => om_1[4]~reg0.CLK
clk => om_1[5]~reg0.CLK
clk => acs_1~reg0.CLK
reset => acs_1~0.OUTPUTSELECT
reset => om_1~6.OUTPUTSELECT
reset => om_1~7.OUTPUTSELECT
reset => om_1~8.OUTPUTSELECT
reset => om_1~9.OUTPUTSELECT
reset => om_1~10.OUTPUTSELECT
reset => om_1~11.OUTPUTSELECT
rc[0] => mc_2~0.IN0
rc[0] => mc_2~1.IN0
rc[0] => mc_0~1.IN0
rc[0] => mc_0~0.IN0
rc[1] => mc_2~0.IN1
rc[1] => mc_2~1.IN1
rc[1] => mc_0~1.IN1
rc[1] => mc_0~0.IN1
im_0[0] => Add0.IN12
im_0[1] => Add0.IN11
im_0[2] => Add0.IN10
im_0[3] => Add0.IN9
im_0[4] => Add0.IN8
im_0[5] => Add0.IN7
im_2[0] => Add1.IN12
im_2[1] => Add1.IN11
im_2[2] => Add1.IN10
im_2[3] => Add1.IN9
im_2[4] => Add1.IN8
im_2[5] => Add1.IN7
acs_1 <= acs_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[0] <= om_1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[1] <= om_1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[2] <= om_1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[3] <= om_1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[4] <= om_1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
om_1[5] <= om_1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE