tr_dff2.tan.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "ITDB_TSU_RESULT" "out_outp\[1\]~reg0 in_outp\[1\] clk 2.074 ns register " "Info: tsu for register \"out_outp\[1\]~reg0\" (data pin = \"in_outp\[1\]\", clock pin = \"clk\") is 2.074 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.987 ns + Longest pin register " "Info: + Longest pin to register delay is 4.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns in_outp\[1\] 1 PIN PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B12; Fanout = 1; PIN Node = 'in_outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in_outp[1] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.677 ns) + CELL(0.223 ns) 4.987 ns out_outp\[1\]~reg0 2 REG LC_X25_Y30_N2 1 " "Info: 2: + IC(3.677 ns) + CELL(0.223 ns) = 4.987 ns; Loc. = LC_X25_Y30_N2; Fanout = 1; REG Node = 'out_outp\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { in_outp[1] out_outp[1]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 26.27 % ) " "Info: Total cell delay = 1.310 ns ( 26.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.677 ns ( 73.73 % ) " "Info: Total interconnect delay = 3.677 ns ( 73.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.987 ns" { in_outp[1] out_outp[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.987 ns" { in_outp[1] in_outp[1]~out0 out_outp[1]~reg0 } { 0.000ns 0.000ns 3.677ns } { 0.000ns 1.087ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.923 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns out_outp\[1\]~reg0 2 REG LC_X25_Y30_N2 1 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X25_Y30_N2; Fanout = 1; REG Node = 'out_outp\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk out_outp[1]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk out_outp[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 out_outp[1]~reg0 } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.987 ns" { in_outp[1] out_outp[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.987 ns" { in_outp[1] in_outp[1]~out0 out_outp[1]~reg0 } { 0.000ns 0.000ns 3.677ns } { 0.000ns 1.087ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk out_outp[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 out_outp[1]~reg0 } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out_outp\[0\] out_outp\[0\]~reg0 6.726 ns register " "Info: tco from clock \"clk\" to destination pin \"out_outp\[0\]\" through register \"out_outp\[0\]~reg0\" is 6.726 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns out_outp\[0\]~reg0 2 REG LC_X5_Y1_N2 1 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'out_outp\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.561 ns + Longest register pin " "Info: + Longest register to pin delay is 3.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out_outp\[0\]~reg0 1 REG LC_X5_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'out_outp\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out_outp[0]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(2.404 ns) 3.561 ns out_outp\[0\] 2 PIN PIN_V18 0 " "Info: 2: + IC(1.157 ns) + CELL(2.404 ns) = 3.561 ns; Loc. = PIN_V18; Fanout = 0; PIN Node = 'out_outp\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.561 ns" { out_outp[0]~reg0 out_outp[0] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.51 % ) " "Info: Total cell delay = 2.404 ns ( 67.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 32.49 % ) " "Info: Total interconnect delay = 1.157 ns ( 32.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.561 ns" { out_outp[0]~reg0 out_outp[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.561 ns" { out_outp[0]~reg0 out_outp[0] } { 0.000ns 1.157ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.561 ns" { out_outp[0]~reg0 out_outp[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.561 ns" { out_outp[0]~reg0 out_outp[0] } { 0.000ns 1.157ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "out_outp\[0\]~reg0 in_outp\[0\] clk -1.747 ns register " "Info: th for register \"out_outp\[0\]~reg0\" (data pin = \"in_outp\[0\]\", clock pin = \"clk\") is -1.747 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns out_outp\[0\]~reg0 2 REG LC_X5_Y1_N2 1 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'out_outp\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.856 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns in_outp\[0\] 1 PIN PIN_AB18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB18; Fanout = 1; PIN Node = 'in_outp\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in_outp[0] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.684 ns) + CELL(0.085 ns) 4.856 ns out_outp\[0\]~reg0 2 REG LC_X5_Y1_N2 1 " "Info: 2: + IC(3.684 ns) + CELL(0.085 ns) = 4.856 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'out_outp\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.769 ns" { in_outp[0] out_outp[0]~reg0 } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns ( 24.14 % ) " "Info: Total cell delay = 1.172 ns ( 24.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.684 ns ( 75.86 % ) " "Info: Total interconnect delay = 3.684 ns ( 75.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.856 ns" { in_outp[0] out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.856 ns" { in_outp[0] in_outp[0]~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 3.684ns } { 0.000ns 1.087ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.856 ns" { in_outp[0] out_outp[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.856 ns" { in_outp[0] in_outp[0]~out0 out_outp[0]~reg0 } { 0.000ns 0.000ns 3.684ns } { 0.000ns 1.087ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 02 13:08:17 2006 " "Info: Processing ended: Mon Oct 02 13:08:17 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}