acs_1.tan.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "ITDB_TSU_RESULT" "om_1\[0\]~reg0 rc\[0\] clk 7.362 ns register " "Info: tsu for register \"om_1\[0\]~reg0\" (data pin = \"rc\[0\]\", clock pin = \"clk\") is 7.362 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.285 ns + Longest pin register " "Info: + Longest pin to register delay is 10.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns rc\[0\] 1 PIN PIN_G16 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G16; Fanout = 3; PIN Node = 'rc\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rc[0] } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.915 ns) + CELL(0.183 ns) 5.185 ns mc_0~1 2 COMB LC_X7_Y30_N7 3 " "Info: 2: + IC(3.915 ns) + CELL(0.183 ns) = 5.185 ns; Loc. = LC_X7_Y30_N7; Fanout = 3; COMB Node = 'mc_0~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.098 ns" { rc[0] mc_0~1 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.443 ns) 6.615 ns Add0~92 3 COMB LC_X7_Y27_N2 2 " "Info: 3: + IC(0.987 ns) + CELL(0.443 ns) = 6.615 ns; Loc. = LC_X7_Y27_N2; Fanout = 2; COMB Node = 'Add0~92'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.430 ns" { mc_0~1 Add0~92 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 6.673 ns Add0~94 4 COMB LC_X7_Y27_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 6.673 ns; Loc. = LC_X7_Y27_N3; Fanout = 2; COMB Node = 'Add0~94'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { Add0~92 Add0~94 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 6.803 ns Add0~96 5 COMB LC_X7_Y27_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.130 ns) = 6.803 ns; Loc. = LC_X7_Y27_N4; Fanout = 2; COMB Node = 'Add0~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.130 ns" { Add0~94 Add0~96 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 7.252 ns Add0~97 6 COMB LC_X7_Y27_N5 3 " "Info: 6: + IC(0.000 ns) + CELL(0.449 ns) = 7.252 ns; Loc. = LC_X7_Y27_N5; Fanout = 3; COMB Node = 'Add0~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.449 ns" { Add0~96 Add0~97 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.451 ns) 8.664 ns om_1\[4\]~28COUT1_33 7 COMB LC_X7_Y29_N5 1 " "Info: 7: + IC(0.961 ns) + CELL(0.451 ns) = 8.664 ns; Loc. = LC_X7_Y29_N5; Fanout = 1; COMB Node = 'om_1\[4\]~28COUT1_33'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.412 ns" { Add0~97 om_1[4]~28COUT1_33 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 8.724 ns om_1\[5\]~29COUT1_34 8 COMB LC_X7_Y29_N6 1 " "Info: 8: + IC(0.000 ns) + CELL(0.060 ns) = 8.724 ns; Loc. = LC_X7_Y29_N6; Fanout = 1; COMB Node = 'om_1\[5\]~29COUT1_34'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { om_1[4]~28COUT1_33 om_1[5]~29COUT1_34 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 9.089 ns LessThan0~25 9 COMB LC_X7_Y29_N7 7 " "Info: 9: + IC(0.000 ns) + CELL(0.365 ns) = 9.089 ns; Loc. = LC_X7_Y29_N7; Fanout = 7; COMB Node = 'LessThan0~25'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { om_1[5]~29COUT1_34 LessThan0~25 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.870 ns) 10.285 ns om_1\[0\]~reg0 10 REG LC_X7_Y29_N1 1 " "Info: 10: + IC(0.326 ns) + CELL(0.870 ns) = 10.285 ns; Loc. = LC_X7_Y29_N1; Fanout = 1; REG Node = 'om_1\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.196 ns" { LessThan0~25 om_1[0]~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.096 ns ( 39.82 % ) " "Info: Total cell delay = 4.096 ns ( 39.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.189 ns ( 60.18 % ) " "Info: Total interconnect delay = 6.189 ns ( 60.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.285 ns" { rc[0] mc_0~1 Add0~92 Add0~94 Add0~96 Add0~97 om_1[4]~28COUT1_33 om_1[5]~29COUT1_34 LessThan0~25 om_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.285 ns" { rc[0] rc[0]~out0 mc_0~1 Add0~92 Add0~94 Add0~96 Add0~97 om_1[4]~28COUT1_33 om_1[5]~29COUT1_34 LessThan0~25 om_1[0]~reg0 } { 0.000ns 0.000ns 3.915ns 0.987ns 0.000ns 0.000ns 0.000ns 0.961ns 0.000ns 0.000ns 0.326ns } { 0.000ns 1.087ns 0.183ns 0.443ns 0.058ns 0.130ns 0.449ns 0.451ns 0.060ns 0.365ns 0.870ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.933 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.563 ns) + CELL(0.542 ns) 2.933 ns om_1\[0\]~reg0 2 REG LC_X7_Y29_N1 1 " "Info: 2: + IC(1.563 ns) + CELL(0.542 ns) = 2.933 ns; Loc. = LC_X7_Y29_N1; Fanout = 1; REG Node = 'om_1\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.105 ns" { clk om_1[0]~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.71 % ) " "Info: Total cell delay = 1.370 ns ( 46.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.563 ns ( 53.29 % ) " "Info: Total interconnect delay = 1.563 ns ( 53.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk om_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 om_1[0]~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.285 ns" { rc[0] mc_0~1 Add0~92 Add0~94 Add0~96 Add0~97 om_1[4]~28COUT1_33 om_1[5]~29COUT1_34 LessThan0~25 om_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.285 ns" { rc[0] rc[0]~out0 mc_0~1 Add0~92 Add0~94 Add0~96 Add0~97 om_1[4]~28COUT1_33 om_1[5]~29COUT1_34 LessThan0~25 om_1[0]~reg0 } { 0.000ns 0.000ns 3.915ns 0.987ns 0.000ns 0.000ns 0.000ns 0.961ns 0.000ns 0.000ns 0.326ns } { 0.000ns 1.087ns 0.183ns 0.443ns 0.058ns 0.130ns 0.449ns 0.451ns 0.060ns 0.365ns 0.870ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk om_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 om_1[0]~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk om_1\[2\] om_1\[2\]~reg0 6.915 ns register " "Info: tco from clock \"clk\" to destination pin \"om_1\[2\]\" through register \"om_1\[2\]~reg0\" is 6.915 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.933 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.563 ns) + CELL(0.542 ns) 2.933 ns om_1\[2\]~reg0 2 REG LC_X7_Y29_N3 1 " "Info: 2: + IC(1.563 ns) + CELL(0.542 ns) = 2.933 ns; Loc. = LC_X7_Y29_N3; Fanout = 1; REG Node = 'om_1\[2\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.105 ns" { clk om_1[2]~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.71 % ) " "Info: Total cell delay = 1.370 ns ( 46.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.563 ns ( 53.29 % ) " "Info: Total interconnect delay = 1.563 ns ( 53.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk om_1[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 om_1[2]~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.826 ns + Longest register pin " "Info: + Longest register to pin delay is 3.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns om_1\[2\]~reg0 1 REG LC_X7_Y29_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y29_N3; Fanout = 1; REG Node = 'om_1\[2\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { om_1[2]~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.422 ns) + CELL(2.404 ns) 3.826 ns om_1\[2\] 2 PIN PIN_B15 0 " "Info: 2: + IC(1.422 ns) + CELL(2.404 ns) = 3.826 ns; Loc. = PIN_B15; Fanout = 0; PIN Node = 'om_1\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { om_1[2]~reg0 om_1[2] } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 62.83 % ) " "Info: Total cell delay = 2.404 ns ( 62.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.422 ns ( 37.17 % ) " "Info: Total interconnect delay = 1.422 ns ( 37.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { om_1[2]~reg0 om_1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.826 ns" { om_1[2]~reg0 om_1[2] } { 0.000ns 1.422ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk om_1[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 om_1[2]~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { om_1[2]~reg0 om_1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.826 ns" { om_1[2]~reg0 om_1[2] } { 0.000ns 1.422ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "acs_1~reg0 reset clk -2.194 ns register " "Info: th for register \"acs_1~reg0\" (data pin = \"reset\", clock pin = \"clk\") is -2.194 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.933 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.563 ns) + CELL(0.542 ns) 2.933 ns acs_1~reg0 2 REG LC_X7_Y29_N8 1 " "Info: 2: + IC(1.563 ns) + CELL(0.542 ns) = 2.933 ns; Loc. = LC_X7_Y29_N8; Fanout = 1; REG Node = 'acs_1~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.105 ns" { clk acs_1~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.71 % ) " "Info: Total cell delay = 1.370 ns ( 46.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.563 ns ( 53.29 % ) " "Info: Total interconnect delay = 1.563 ns ( 53.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk acs_1~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 acs_1~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.227 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.227 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns reset 1 PIN PIN_B18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B18; Fanout = 7; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.821 ns) + CELL(0.319 ns) 5.227 ns acs_1~reg0 2 REG LC_X7_Y29_N8 1 " "Info: 2: + IC(3.821 ns) + CELL(0.319 ns) = 5.227 ns; Loc. = LC_X7_Y29_N8; Fanout = 1; REG Node = 'acs_1~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.140 ns" { reset acs_1~reg0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns ( 26.90 % ) " "Info: Total cell delay = 1.406 ns ( 26.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.821 ns ( 73.10 % ) " "Info: Total interconnect delay = 3.821 ns ( 73.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.227 ns" { reset acs_1~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.227 ns" { reset reset~out0 acs_1~reg0 } { 0.000ns 0.000ns 3.821ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.933 ns" { clk acs_1~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.933 ns" { clk clk~out0 acs_1~reg0 } { 0.000ns 0.000ns 1.563ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.227 ns" { reset acs_1~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.227 ns" { reset reset~out0 acs_1~reg0 } { 0.000ns 0.000ns 3.821ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 02 14:49:18 2006 " "Info: Processing ended: Mon Oct 02 14:49:18 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}