dec_copy.fit.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.249 ns register register " "Info: Estimated most critical path is register to register delay of 6.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ACS_3:inst6\|om_3\[0\] 1 REG LAB_X19_Y9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y9; Fanout = 7; REG Node = 'ACS_3:inst6\|om_3\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.575 ns) 1.274 ns ACS_2:inst5\|Add1~104COUT1_106 2 COMB LAB_X18_Y9 2 " "Info: 2: + IC(0.699 ns) + CELL(0.575 ns) = 1.274 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~104COUT1_106'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.354 ns ACS_2:inst5\|Add1~102COUT1_107 3 COMB LAB_X18_Y9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.354 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~102COUT1_107'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~102COUT1_107 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.434 ns ACS_2:inst5\|Add1~100COUT1 4 COMB LAB_X18_Y9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.434 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~100COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { ACS_2:inst5|Add1~102COUT1_107 ACS_2:inst5|Add1~100COUT1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.042 ns ACS_2:inst5\|Add1~97 5 COMB LAB_X18_Y9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 2.042 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { ACS_2:inst5|Add1~100COUT1 ACS_2:inst5|Add1~97 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.838 ns) 3.975 ns ACS_2:inst5\|LessThan0~90 6 COMB LAB_X19_Y11 1 " "Info: 6: + IC(1.095 ns) + CELL(0.838 ns) = 3.975 ns; Loc. = LAB_X19_Y11; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~90'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.933 ns" { ACS_2:inst5|Add1~97 ACS_2:inst5|LessThan0~90 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 4.654 ns ACS_2:inst5\|LessThan0~78 7 COMB LAB_X19_Y11 7 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 4.654 ns; Loc. = LAB_X19_Y11; Fanout = 7; COMB Node = 'ACS_2:inst5\|LessThan0~78'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.309 ns) 6.249 ns ACS_2:inst5\|om_2\[5\] 8 REG LAB_X20_Y10 3 " "Info: 8: + IC(1.286 ns) + CELL(0.309 ns) = 6.249 ns; Loc. = LAB_X20_Y10; Fanout = 3; REG Node = 'ACS_2:inst5\|om_2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.595 ns" { ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.169 ns ( 50.71 % ) " "Info: Total cell delay = 3.169 ns ( 50.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.080 ns ( 49.29 % ) " "Info: Total interconnect delay = 3.080 ns ( 49.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.249 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~102COUT1_107 ACS_2:inst5|Add1~100COUT1 ACS_2:inst5|Add1~97 ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 12 15:09:25 2006 " "Info: Processing ended: Thu Oct 12 15:09:25 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/My viterbi/viterbi213/dec_copy.fit.smsg " "Info: Generated suppressed messages file E:/My viterbi/viterbi213/dec_copy.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}