omet.tan.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "ITDB_TSU_RESULT" "omet_3\[2\]~reg0 reset clk 3.392 ns register " "Info: tsu for register \"omet_3\[2\]~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 3.392 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.247 ns + Longest pin register " "Info: + Longest pin to register delay is 6.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns reset 1 PIN PIN_C12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C12; Fanout = 24; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.621 ns) + CELL(0.539 ns) 6.247 ns omet_3\[2\]~reg0 2 REG LC_X52_Y27_N2 1 " "Info: 2: + IC(4.621 ns) + CELL(0.539 ns) = 6.247 ns; Loc. = LC_X52_Y27_N2; Fanout = 1; REG Node = 'omet_3\[2\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.160 ns" { reset omet_3[2]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 26.03 % ) " "Info: Total cell delay = 1.626 ns ( 26.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.621 ns ( 73.97 % ) " "Info: Total interconnect delay = 4.621 ns ( 73.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.247 ns" { reset omet_3[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.247 ns" { reset reset~out0 omet_3[2]~reg0 } { 0.000ns 0.000ns 4.621ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.865 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.495 ns) + CELL(0.542 ns) 2.865 ns omet_3\[2\]~reg0 2 REG LC_X52_Y27_N2 1 " "Info: 2: + IC(1.495 ns) + CELL(0.542 ns) = 2.865 ns; Loc. = LC_X52_Y27_N2; Fanout = 1; REG Node = 'omet_3\[2\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.037 ns" { clk omet_3[2]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.82 % ) " "Info: Total cell delay = 1.370 ns ( 47.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.495 ns ( 52.18 % ) " "Info: Total interconnect delay = 1.495 ns ( 52.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk omet_3[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~out0 omet_3[2]~reg0 } { 0.000ns 0.000ns 1.495ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.247 ns" { reset omet_3[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.247 ns" { reset reset~out0 omet_3[2]~reg0 } { 0.000ns 0.000ns 4.621ns } { 0.000ns 1.087ns 0.539ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk omet_3[2]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~out0 omet_3[2]~reg0 } { 0.000ns 0.000ns 1.495ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk omet_1\[0\] omet_1\[0\]~reg0 7.088 ns register " "Info: tco from clock \"clk\" to destination pin \"omet_1\[0\]\" through register \"omet_1\[0\]~reg0\" is 7.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns omet_1\[0\]~reg0 2 REG LC_X1_Y30_N8 1 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 1; REG Node = 'omet_1\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk omet_1[0]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk omet_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 omet_1[0]~reg0 } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.998 ns + Longest register pin " "Info: + Longest register to pin delay is 3.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns omet_1\[0\]~reg0 1 REG LC_X1_Y30_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N8; Fanout = 1; REG Node = 'omet_1\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { omet_1[0]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(2.376 ns) 3.998 ns omet_1\[0\] 2 PIN PIN_H17 0 " "Info: 2: + IC(1.622 ns) + CELL(2.376 ns) = 3.998 ns; Loc. = PIN_H17; Fanout = 0; PIN Node = 'omet_1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.998 ns" { omet_1[0]~reg0 omet_1[0] } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 59.43 % ) " "Info: Total cell delay = 2.376 ns ( 59.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.622 ns ( 40.57 % ) " "Info: Total interconnect delay = 1.622 ns ( 40.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.998 ns" { omet_1[0]~reg0 omet_1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.998 ns" { omet_1[0]~reg0 omet_1[0] } { 0.000ns 1.622ns } { 0.000ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk omet_1[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 omet_1[0]~reg0 } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.998 ns" { omet_1[0]~reg0 omet_1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.998 ns" { omet_1[0]~reg0 omet_1[0] } { 0.000ns 1.622ns } { 0.000ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "omet_0\[4\]~reg0 imet_0\[4\] clk -1.599 ns register " "Info: th for register \"omet_0\[4\]~reg0\" (data pin = \"imet_0\[4\]\", clock pin = \"clk\") is -1.599 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns omet_0\[4\]~reg0 2 REG LC_X1_Y30_N9 1 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N9; Fanout = 1; REG Node = 'omet_0\[4\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk omet_0[4]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk omet_0[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 omet_0[4]~reg0 } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.633 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.633 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns imet_0\[4\] 1 PIN PIN_E19 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E19; Fanout = 1; PIN Node = 'imet_0\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { imet_0[4] } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.176 ns) + CELL(0.223 ns) 4.633 ns omet_0\[4\]~reg0 2 REG LC_X1_Y30_N9 1 " "Info: 2: + IC(3.176 ns) + CELL(0.223 ns) = 4.633 ns; Loc. = LC_X1_Y30_N9; Fanout = 1; REG Node = 'omet_0\[4\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.399 ns" { imet_0[4] omet_0[4]~reg0 } "NODE_NAME" } } { "omet.vhd" "" { Text "E:/viterbi213/omet.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 31.45 % ) " "Info: Total cell delay = 1.457 ns ( 31.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.176 ns ( 68.55 % ) " "Info: Total interconnect delay = 3.176 ns ( 68.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.633 ns" { imet_0[4] omet_0[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.633 ns" { imet_0[4] imet_0[4]~out0 omet_0[4]~reg0 } { 0.000ns 0.000ns 3.176ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk omet_0[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 omet_0[4]~reg0 } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.633 ns" { imet_0[4] omet_0[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.633 ns" { imet_0[4] imet_0[4]~out0 omet_0[4]~reg0 } { 0.000ns 0.000ns 3.176ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 04 22:07:53 2006 " "Info: Processing ended: Wed Oct 04 22:07:53 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}