output_design.vhd

来自「提供了一个硬判决的viterbi译码器（2」· VHDL 代码 · 共 22 行

--output design
--v0.1

library ieee;
use ieee.std_logic_1164.all;

entity output_design is
	port(
		sout0: in std_logic;
		sout1: in std_logic;
		sout2: in std_logic;
		sout3: in std_logic;
		dec_out: out std_logic
		);
end output_design;

architecture a of output_design is
begin
	dec_out<=(sout0 and sout1 and sout2) or (sout0 and sout1 and sout3) 
				or (sout1 and sout2 and sout3) or (sout0 and sout1 and sout2 and sout3);	
end a;