dec.map.rpt

提供了一个硬判决的viterbi译码器（2

; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 135   ;
;     -- Combinational with no register       ; 73    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 62    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 1     ;
;     -- 3 input functions                    ; 74    ;
;     -- 2 input functions                    ; 58    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 74    ;
;     -- arithmetic mode                      ; 61    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 56    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 62    ;
; Total logic cells in carry chains           ; 73    ;
; I/O pins                                    ; 77    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 62    ;
; Total fan-out                               ; 537   ;
; Average fan-out                             ; 2.53  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                  ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; |dec                       ; 135 (0)     ; 62           ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 77   ; 0            ; 73 (0)       ; 0 (0)             ; 62 (0)           ; 73 (0)          ; 0 (0)      ; |dec                     ;
;    |ACS_0:inst3|           ; 20 (20)     ; 7            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 7 (7)            ; 19 (19)         ; 0 (0)      ; |dec|ACS_0:inst3         ;
;    |ACS_1:inst4|           ; 27 (27)     ; 7            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 7 (7)            ; 18 (18)         ; 0 (0)      ; |dec|ACS_1:inst4         ;
;    |ACS_2:inst5|           ; 25 (25)     ; 7            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 7 (7)            ; 18 (18)         ; 0 (0)      ; |dec|ACS_2:inst5         ;
;    |ACS_3:inst6|           ; 28 (28)     ; 7            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 21 (21)      ; 0 (0)             ; 7 (7)            ; 18 (18)         ; 0 (0)      ; |dec|ACS_3:inst6         ;
;    |output_design:inst1|   ; 1 (1)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |dec|output_design:inst1 ;
;    |reg_exchange:inst|     ; 34 (34)     ; 34           ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 34 (34)          ; 0 (0)           ; 0 (0)      ; |dec|reg_exchange:inst   ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 62    ;
; Number of registers using Synchronous Clear  ; 53    ;
; Number of registers using Synchronous Load   ; 9     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |dec|reg_exchange:inst|w0[9] ;
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |dec|reg_exchange:inst|w1[9] ;
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |dec|reg_exchange:inst|w2[9] ;
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |dec|reg_exchange:inst|w3[9] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Oct 06 15:31:03 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dec -c dec
Warning: Using design file dec.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dec
Info: Elaborating entity "dec" for the top level hierarchy
Warning: Using design file reg_exchange.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: reg_exchange-a
    Info: Found entity 1: reg_exchange
Info: Elaborating entity "reg_exchange" for hierarchy "reg_exchange:inst"
Warning: Using design file ACS_0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ACS_0-a
    Info: Found entity 1: ACS_0
Info: Elaborating entity "ACS_0" for hierarchy "ACS_0:inst3"
Warning: Using design file ACS_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ACS_2-a
    Info: Found entity 1: ACS_2
Info: Elaborating entity "ACS_2" for hierarchy "ACS_2:inst5"
Warning: Using design file ACS_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ACS_1-a
    Info: Found entity 1: ACS_1
Info: Elaborating entity "ACS_1" for hierarchy "ACS_1:inst4"
Warning: Using design file ACS_3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ACS_3-a
    Info: Found entity 1: ACS_3
Info: Elaborating entity "ACS_3" for hierarchy "ACS_3:inst6"
Warning: Using design file output_design.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: output_design-a
    Info: Found entity 1: output_design
Info: Elaborating entity "output_design" for hierarchy "output_design:inst1"
Warning: Reduced register "reg_exchange:inst|w2[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg_exchange:inst|w0[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg_exchange:inst|w1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "reg_exchange:inst|w0[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "reg_exchange:inst|w1[0]" merged to single register "reg_exchange:inst|w3[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "reg_exchange:inst|w2[1]" merged to single register "reg_exchange:inst|w3[1]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "oreg0[1]" stuck at GND
    Warning: Pin "oreg0[0]" stuck at GND
    Warning: Pin "oreg1[1]" stuck at GND
    Warning: Pin "oreg2[0]" stuck at GND
Info: Implemented 212 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 73 output pins
    Info: Implemented 135 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Processing ended: Fri Oct 06 15:31:08 2006
    Info: Elapsed time: 00:00:06