lcd12864.map.rpt

FPGA驱动LCD12864显示

; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; LCD12864.bdf                     ; yes             ; User Block Diagram/Schematic File  ; F:/Q80/temp/verilog/EP2C5-V5/LCD12864_v/LCD12864.bdf               ;
; newlcd.v                         ; yes             ; User Verilog HDL File              ; F:/Q80/temp/verilog/EP2C5-V5/LCD12864_v/newlcd.v                   ;
; rom.v                            ; yes             ; User Verilog HDL File              ; F:/Q80/temp/verilog/EP2C5-V5/LCD12864_v/rom.v                      ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc        ;
; aglobal80.inc                    ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/aglobal80.inc         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_ov61.tdf           ; yes             ; Auto-Generated Megafunction        ; F:/Q80/temp/verilog/EP2C5-V5/LCD12864_v/db/altsyncram_ov61.tdf     ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 78    ;
;                                             ;       ;
; Total combinational functions               ; 78    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 30    ;
;     -- 3 input functions                    ; 8     ;
;     -- <=2 input functions                  ; 40    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 48    ;
;     -- arithmetic mode                      ; 30    ;
;                                             ;       ;
; Total registers                             ; 41    ;
;     -- Dedicated logic registers            ; 41    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 17    ;
; Total memory bits                           ; 16384 ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 49    ;
; Total fan-out                               ; 470   ;
; Average fan-out                             ; 3.26  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                          ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+--------------+
; |LCD12864                                    ; 78 (0)            ; 41 (0)       ; 16384       ; 0            ; 0       ; 0         ; 17   ; 0            ; |LCD12864                                                                                    ; work         ;
;    |newlcd:inst|                             ; 78 (78)           ; 41 (41)      ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LCD12864|newlcd:inst                                                                        ; work         ;
;       |rom:rom|                              ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LCD12864|newlcd:inst|rom:rom                                                                ; work         ;
;          |altsyncram:altsyncram_component|   ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LCD12864|newlcd:inst|rom:rom|altsyncram:altsyncram_component                                ; work         ;
;             |altsyncram_ov61:auto_generated| ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LCD12864|newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated ; work         ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                           ;
+-----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------+
; Name                                                                                          ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF      ;
+-----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------+
; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 2048         ; 8            ; --           ; --           ; 16384 ; char.hex ;
+-----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |LCD12864|newlcd:inst|state                                                                                                                                                                                             ;
+----------------------+---------------------+---------------------+-----------------+----------------------+-----------------+----------------------+-----------------+-----------------+-----------------+-----------------+------------+
; Name                 ; state.SETrow_addr_2 ; state.SETrow_addr_1 ; state.wr_data_2 ; state.SETpage_addr_1 ; state.setmode_2 ; state.SETpage_addr_2 ; state.wr_data_1 ; state.setbase_2 ; state.setmode_1 ; state.setbase_1 ; state.idle ;
+----------------------+---------------------+---------------------+-----------------+----------------------+-----------------+----------------------+-----------------+-----------------+-----------------+-----------------+------------+
; state.idle           ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0          ;
; state.setbase_1      ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 1               ; 1          ;
; state.setmode_1      ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 1               ; 0               ; 1          ;
; state.setbase_2      ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 1               ; 0               ; 0               ; 1          ;
; state.wr_data_1      ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 1               ; 0               ; 0               ; 0               ; 1          ;
; state.SETpage_addr_2 ; 0                   ; 0                   ; 0               ; 0                    ; 0               ; 1                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.setmode_2      ; 0                   ; 0                   ; 0               ; 0                    ; 1               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.SETpage_addr_1 ; 0                   ; 0                   ; 0               ; 1                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.wr_data_2      ; 0                   ; 0                   ; 1               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.SETrow_addr_1  ; 0                   ; 1                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.SETrow_addr_2  ; 1                   ; 0                   ; 0               ; 0                    ; 0               ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1          ;
+----------------------+---------------------+---------------------+-----------------+----------------------+-----------------+----------------------+-----------------+-----------------+-----------------+-----------------+------------+


+--------------------------------------------------------------------------+
; Registers Removed During Synthesis                                       ;
+----------------------------------------+---------------------------------+
; Register name                          ; Reason for Removal              ;
+----------------------------------------+---------------------------------+
; newlcd:inst|cs_r[0]                    ; Merged with newlcd:inst|cs_r[1] ;
; newlcd:inst|state~121                  ; Lost fanout                     ;
; newlcd:inst|state~122                  ; Lost fanout                     ;
; newlcd:inst|state~123                  ; Lost fanout                     ;
; newlcd:inst|state~124                  ; Lost fanout                     ;
; newlcd:inst|div_cnt[16..20]            ; Lost fanout                     ;
; Total Number of Removed Registers = 10 ;                                 ;
+----------------------------------------+---------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 41    ;
; Number of registers using Synchronous Clear  ; 10    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 31    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 21    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 5:1                ; 3 bits    ; 9 LEs         ; 9 LEs                ; 0 LEs                  ; No         ; |LCD12864|newlcd:inst|Selector7 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+