lcd12864.tan.rpt
来自「FPGA驱动LCD12864显示」· RPT 代码 · 共 216 行 · 第 1/5 页
RPT
216 行
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[4] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg9 ; clk ; clk ; None ; None ; 4.111 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[3] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg5 ; clk ; clk ; None ; None ; 4.103 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg8 ; clk ; clk ; None ; None ; 4.098 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[5] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg9 ; clk ; clk ; None ; None ; 4.094 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[3] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg4 ; clk ; clk ; None ; None ; 4.094 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[8] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg10 ; clk ; clk ; None ; None ; 4.099 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg7 ; clk ; clk ; None ; None ; 4.092 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[9] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg10 ; clk ; clk ; None ; None ; 4.080 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[4] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg5 ; clk ; clk ; None ; None ; 4.078 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[4] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg8 ; clk ; clk ; None ; None ; 4.076 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[5] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg9 ; clk ; clk ; None ; None ; 4.070 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg7 ; clk ; clk ; None ; None ; 4.058 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[4] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg5 ; clk ; clk ; None ; None ; 4.037 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[5] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg8 ; clk ; clk ; None ; None ; 4.035 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[8] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg9 ; clk ; clk ; None ; None ; 4.030 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[9] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg10 ; clk ; clk ; None ; None ; 4.028 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[8] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg8 ; clk ; clk ; None ; None ; 4.023 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[3] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg7 ; clk ; clk ; None ; None ; 4.022 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[9] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg10 ; clk ; clk ; None ; None ; 4.019 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[3] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg4 ; clk ; clk ; None ; None ; 3.996 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[7] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg8 ; clk ; clk ; None ; None ; 3.989 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[4] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg7 ; clk ; clk ; None ; None ; 3.956 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[5] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg7 ; clk ; clk ; None ; None ; 3.915 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg9 ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg9 ; clk ; clk ; None ; None ; 3.847 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[6] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg8 ; clk ; clk ; None ; None ; 3.812 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[7] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a4~porta_address_reg9 ; clk ; clk ; None ; None ; 3.762 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[7] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg9 ; clk ; clk ; None ; None ; 3.738 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|cnt[3] ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a2~porta_address_reg5 ; clk ; clk ; None ; None ; 3.735 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg1 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg2 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg3 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg4 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg5 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg6 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg7 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg8 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg9 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|ram_block1a6~porta_address_reg10 ; newlcd:inst|rom:rom|altsyncram:altsyncram_component|altsyncram_ov61:auto_generated|q_a[6] ; clk ; clk ; None ; None ; 3.641 ns ;
; N/A ; Restricted ⌨️ 快捷键说明
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