8x8led

来自「CPLD的小程序集合」· 代码 · 共 331 行 · 第 1/3 页

; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; cnt_scan[5]  ; cnt_scan[5]  ; clk        ; clk      ; None                        ; None                      ; 1.953 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; cnt_scan[0]  ; cnt_scan[0]  ; clk        ; clk      ; None                        ; None                      ; 1.513 ns                ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+--------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To         ; From Clock ;
+-------+--------------+------------+--------------+------------+------------+
; N/A   ; None         ; 10.524 ns  ; cnt_scan[15] ; en[0]      ; clk        ;
; N/A   ; None         ; 10.374 ns  ; cnt_scan[15] ; en[1]      ; clk        ;
; N/A   ; None         ; 10.367 ns  ; cnt_scan[15] ; en[6]      ; clk        ;
; N/A   ; None         ; 10.367 ns  ; cnt_scan[14] ; en[0]      ; clk        ;
; N/A   ; None         ; 10.344 ns  ; cnt_scan[15] ; en[3]      ; clk        ;
; N/A   ; None         ; 10.328 ns  ; cnt_scan[15] ; en[2]      ; clk        ;
; N/A   ; None         ; 10.317 ns  ; cnt_scan[15] ; en[5]      ; clk        ;
; N/A   ; None         ; 10.216 ns  ; cnt_scan[14] ; en[1]      ; clk        ;
; N/A   ; None         ; 10.210 ns  ; cnt_scan[14] ; en[6]      ; clk        ;
; N/A   ; None         ; 10.186 ns  ; cnt_scan[14] ; en[3]      ; clk        ;
; N/A   ; None         ; 10.170 ns  ; cnt_scan[14] ; en[2]      ; clk        ;
; N/A   ; None         ; 10.153 ns  ; cnt_scan[14] ; en[5]      ; clk        ;
; N/A   ; None         ; 10.116 ns  ; cnt_scan[15] ; dataout[7] ; clk        ;
; N/A   ; None         ; 10.048 ns  ; cnt_scan[14] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.960 ns   ; cnt_scan[14] ; dataout[7] ; clk        ;
; N/A   ; None         ; 9.949 ns   ; cnt_scan[13] ; dataout[7] ; clk        ;
; N/A   ; None         ; 9.937 ns   ; cnt_scan[13] ; en[0]      ; clk        ;
; N/A   ; None         ; 9.838 ns   ; cnt_scan[15] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.787 ns   ; cnt_scan[13] ; en[1]      ; clk        ;
; N/A   ; None         ; 9.780 ns   ; cnt_scan[13] ; en[6]      ; clk        ;
; N/A   ; None         ; 9.758 ns   ; cnt_scan[13] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.741 ns   ; cnt_scan[13] ; en[2]      ; clk        ;
; N/A   ; None         ; 9.726 ns   ; cnt_scan[13] ; en[5]      ; clk        ;
; N/A   ; None         ; 9.684 ns   ; cnt_scan[15] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.682 ns   ; cnt_scan[14] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.671 ns   ; cnt_scan[13] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.670 ns   ; cnt_scan[15] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.658 ns   ; cnt_scan[15] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.528 ns   ; cnt_scan[14] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.517 ns   ; cnt_scan[13] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.501 ns   ; cnt_scan[14] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.071 ns   ; cnt_scan[13] ; dataout[1] ; clk        ;
; N/A   ; None         ; 8.971 ns   ; cnt_scan[15] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.962 ns   ; cnt_scan[15] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.843 ns   ; cnt_scan[14] ; dataout[2] ; clk        ;
; N/A   ; None         ; 8.813 ns   ; cnt_scan[14] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.804 ns   ; cnt_scan[14] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.459 ns   ; cnt_scan[15] ; dataout[2] ; clk        ;
; N/A   ; None         ; 8.383 ns   ; cnt_scan[13] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.376 ns   ; cnt_scan[13] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.083 ns   ; cnt_scan[15] ; dataout[4] ; clk        ;
+-------+--------------+------------+--------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Feb 16 22:20:08 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg70 -c seg70
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 201.09 MHz between source register "cnt_scan[3]" and destination register "cnt_scan[12]" (period= 4.973 ns)
    Info: + Longest register to register delay is 4.264 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X5_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan[3]~82'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X5_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan[4]~81'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X5_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan[5]~80'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X5_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan[6]~79'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X5_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan[7]~78'
        Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X6_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
        Info: Total cell delay = 3.372 ns ( 79.08 % )
        Info: Total interconnect delay = 0.892 ns ( 20.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "en[0]" through register "cnt_scan[15]" is 10.524 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N7; Fanout = 14; REG Node = 'cnt_scan[15]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N7; Fanout = 14; REG Node = 'cnt_scan[15]'
        Info: 2: + IC(1.584 ns) + CELL(0.740 ns) = 2.324 ns; Loc. = LC_X7_Y4_N1; Fanout = 2; COMB Node = 'Mux7~120'
        Info: 3: + IC(2.154 ns) + CELL(2.322 ns) = 6.800 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'en[0]'
        Info: Total cell delay = 3.062 ns ( 45.03 % )
        Info: Total interconnect delay = 3.738 ns ( 54.97 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Feb 16 22:20:08 2009
    Info: Elapsed time: 00:00:01