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来自「CPLD的小程序集合」· 代码 · 共 144 行

Timing Analyzer report for add
Tue Jun 24 23:16:10 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.128 ns   ; b[2] ; c[7] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 10.128 ns       ; b[2] ; c[7] ;
; N/A   ; None              ; 10.116 ns       ; b[2] ; c[4] ;
; N/A   ; None              ; 10.099 ns       ; b[2] ; c[1] ;
; N/A   ; None              ; 10.077 ns       ; a[0] ; c[4] ;
; N/A   ; None              ; 10.073 ns       ; a[0] ; c[1] ;
; N/A   ; None              ; 10.060 ns       ; a[0] ; c[7] ;
; N/A   ; None              ; 10.011 ns       ; b[2] ; c[5] ;
; N/A   ; None              ; 10.005 ns       ; b[2] ; c[3] ;
; N/A   ; None              ; 9.999 ns        ; b[2] ; c[6] ;
; N/A   ; None              ; 9.971 ns        ; a[0] ; c[3] ;
; N/A   ; None              ; 9.970 ns        ; a[0] ; c[6] ;
; N/A   ; None              ; 9.952 ns        ; a[0] ; c[5] ;
; N/A   ; None              ; 9.811 ns        ; b[0] ; c[4] ;
; N/A   ; None              ; 9.807 ns        ; b[0] ; c[7] ;
; N/A   ; None              ; 9.807 ns        ; b[0] ; c[1] ;
; N/A   ; None              ; 9.746 ns        ; b[1] ; c[4] ;
; N/A   ; None              ; 9.742 ns        ; b[1] ; c[1] ;
; N/A   ; None              ; 9.704 ns        ; b[0] ; c[3] ;
; N/A   ; None              ; 9.703 ns        ; b[0] ; c[6] ;
; N/A   ; None              ; 9.689 ns        ; b[0] ; c[5] ;
; N/A   ; None              ; 9.647 ns        ; a[2] ; c[7] ;
; N/A   ; None              ; 9.640 ns        ; b[1] ; c[3] ;
; N/A   ; None              ; 9.639 ns        ; b[1] ; c[6] ;
; N/A   ; None              ; 9.635 ns        ; a[2] ; c[4] ;
; N/A   ; None              ; 9.622 ns        ; a[0] ; c[2] ;
; N/A   ; None              ; 9.621 ns        ; b[1] ; c[5] ;
; N/A   ; None              ; 9.618 ns        ; a[2] ; c[1] ;
; N/A   ; None              ; 9.611 ns        ; b[2] ; c[2] ;
; N/A   ; None              ; 9.593 ns        ; a[1] ; c[4] ;
; N/A   ; None              ; 9.589 ns        ; a[1] ; c[1] ;
; N/A   ; None              ; 9.552 ns        ; b[1] ; c[7] ;
; N/A   ; None              ; 9.530 ns        ; a[2] ; c[5] ;
; N/A   ; None              ; 9.524 ns        ; a[2] ; c[3] ;
; N/A   ; None              ; 9.518 ns        ; a[2] ; c[6] ;
; N/A   ; None              ; 9.487 ns        ; a[1] ; c[3] ;
; N/A   ; None              ; 9.486 ns        ; a[1] ; c[6] ;
; N/A   ; None              ; 9.468 ns        ; a[1] ; c[5] ;
; N/A   ; None              ; 9.399 ns        ; a[1] ; c[7] ;
; N/A   ; None              ; 9.291 ns        ; b[1] ; c[2] ;
; N/A   ; None              ; 9.138 ns        ; a[1] ; c[2] ;
; N/A   ; None              ; 9.130 ns        ; a[2] ; c[2] ;
; N/A   ; None              ; 8.878 ns        ; b[0] ; c[2] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:16:09 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[2]" to destination pin "c[7]" is 10.128 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_5; Fanout = 2; PIN Node = 'b[2]'
    Info: 2: + IC(2.804 ns) + CELL(0.511 ns) = 4.447 ns; Loc. = LC_X2_Y3_N5; Fanout = 7; COMB Node = 'Add0~311'
    Info: 3: + IC(0.867 ns) + CELL(0.511 ns) = 5.825 ns; Loc. = LC_X2_Y3_N3; Fanout = 1; COMB Node = 'Mux0~3'
    Info: 4: + IC(1.981 ns) + CELL(2.322 ns) = 10.128 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'c[7]'
    Info: Total cell delay = 4.476 ns ( 44.19 % )
    Info: Total interconnect delay = 5.652 ns ( 55.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jun 24 23:16:10 2008
    Info: Elapsed time: 00:00:01