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Timing Analyzer report for mux
Tue Jun 24 23:14:20 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.813 ns ; c[2] ; d[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 9.813 ns ; c[2] ; d[1] ;
; N/A ; None ; 9.797 ns ; c[0] ; d[1] ;
; N/A ; None ; 9.730 ns ; c[0] ; d[7] ;
; N/A ; None ; 9.729 ns ; c[2] ; d[7] ;
; N/A ; None ; 9.708 ns ; c[2] ; d[2] ;
; N/A ; None ; 9.699 ns ; c[2] ; d[3] ;
; N/A ; None ; 9.693 ns ; c[0] ; d[3] ;
; N/A ; None ; 9.650 ns ; c[2] ; d[5] ;
; N/A ; None ; 9.630 ns ; c[2] ; d[4] ;
; N/A ; None ; 9.615 ns ; c[0] ; d[4] ;
; N/A ; None ; 9.575 ns ; a ; d[1] ;
; N/A ; None ; 9.548 ns ; b[2] ; d[1] ;
; N/A ; None ; 9.508 ns ; a ; d[7] ;
; N/A ; None ; 9.471 ns ; a ; d[3] ;
; N/A ; None ; 9.467 ns ; a ; d[2] ;
; N/A ; None ; 9.464 ns ; b[2] ; d[7] ;
; N/A ; None ; 9.443 ns ; b[2] ; d[2] ;
; N/A ; None ; 9.434 ns ; b[2] ; d[3] ;
; N/A ; None ; 9.412 ns ; a ; d[5] ;
; N/A ; None ; 9.393 ns ; a ; d[4] ;
; N/A ; None ; 9.385 ns ; b[2] ; d[5] ;
; N/A ; None ; 9.365 ns ; b[2] ; d[4] ;
; N/A ; None ; 9.161 ns ; c[0] ; d[2] ;
; N/A ; None ; 9.129 ns ; c[0] ; d[5] ;
; N/A ; None ; 9.089 ns ; c[2] ; d[6] ;
; N/A ; None ; 9.055 ns ; b[0] ; d[1] ;
; N/A ; None ; 8.989 ns ; b[1] ; d[2] ;
; N/A ; None ; 8.988 ns ; b[0] ; d[7] ;
; N/A ; None ; 8.951 ns ; b[0] ; d[3] ;
; N/A ; None ; 8.934 ns ; b[1] ; d[5] ;
; N/A ; None ; 8.873 ns ; b[0] ; d[4] ;
; N/A ; None ; 8.849 ns ; a ; d[6] ;
; N/A ; None ; 8.824 ns ; b[2] ; d[6] ;
; N/A ; None ; 8.766 ns ; c[1] ; d[2] ;
; N/A ; None ; 8.711 ns ; c[1] ; d[5] ;
; N/A ; None ; 8.566 ns ; b[1] ; d[1] ;
; N/A ; None ; 8.542 ns ; c[0] ; d[6] ;
; N/A ; None ; 8.447 ns ; b[1] ; d[3] ;
; N/A ; None ; 8.419 ns ; b[0] ; d[2] ;
; N/A ; None ; 8.387 ns ; b[0] ; d[5] ;
; N/A ; None ; 8.384 ns ; b[1] ; d[4] ;
; N/A ; None ; 8.371 ns ; b[1] ; d[6] ;
; N/A ; None ; 8.343 ns ; c[1] ; d[1] ;
; N/A ; None ; 8.224 ns ; c[1] ; d[3] ;
; N/A ; None ; 8.161 ns ; c[1] ; d[4] ;
; N/A ; None ; 8.148 ns ; c[1] ; d[6] ;
; N/A ; None ; 7.918 ns ; b[1] ; d[7] ;
; N/A ; None ; 7.800 ns ; b[0] ; d[6] ;
; N/A ; None ; 7.695 ns ; c[1] ; d[7] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jun 24 23:14:20 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "c[2]" to destination pin "d[1]" is 9.813 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'c[2]'
Info: 2: + IC(2.068 ns) + CELL(0.914 ns) = 4.114 ns; Loc. = LC_X2_Y3_N0; Fanout = 7; COMB Node = 'temp_xhd[2]~56'
Info: 3: + IC(0.881 ns) + CELL(0.511 ns) = 5.506 ns; Loc. = LC_X2_Y3_N6; Fanout = 1; COMB Node = 'Mux6~61'
Info: 4: + IC(1.985 ns) + CELL(2.322 ns) = 9.813 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'd[1]'
Info: Total cell delay = 4.879 ns ( 49.72 % )
Info: Total interconnect delay = 4.934 ns ( 50.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Jun 24 23:14:20 2008
Info: Elapsed time: 00:00:01
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