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Timing Analyzer report for sub
Tue Jun 24 23:16:59 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.608 ns ; b[1] ; c[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240GT100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.608 ns ; b[1] ; c[7] ;
; N/A ; None ; 11.582 ns ; b[1] ; c[3] ;
; N/A ; None ; 11.578 ns ; b[1] ; c[1] ;
; N/A ; None ; 11.548 ns ; b[1] ; c[4] ;
; N/A ; None ; 11.463 ns ; a[2] ; c[4] ;
; N/A ; None ; 11.390 ns ; a[0] ; c[7] ;
; N/A ; None ; 11.364 ns ; a[0] ; c[3] ;
; N/A ; None ; 11.360 ns ; a[0] ; c[1] ;
; N/A ; None ; 11.330 ns ; a[0] ; c[4] ;
; N/A ; None ; 11.007 ns ; a[1] ; c[7] ;
; N/A ; None ; 10.981 ns ; a[1] ; c[3] ;
; N/A ; None ; 10.977 ns ; a[1] ; c[1] ;
; N/A ; None ; 10.947 ns ; a[1] ; c[4] ;
; N/A ; None ; 10.906 ns ; b[1] ; c[2] ;
; N/A ; None ; 10.904 ns ; b[1] ; c[5] ;
; N/A ; None ; 10.855 ns ; a[2] ; c[7] ;
; N/A ; None ; 10.830 ns ; a[2] ; c[3] ;
; N/A ; None ; 10.825 ns ; a[2] ; c[1] ;
; N/A ; None ; 10.821 ns ; a[2] ; c[2] ;
; N/A ; None ; 10.819 ns ; a[2] ; c[5] ;
; N/A ; None ; 10.784 ns ; b[2] ; c[4] ;
; N/A ; None ; 10.688 ns ; a[0] ; c[2] ;
; N/A ; None ; 10.686 ns ; a[0] ; c[5] ;
; N/A ; None ; 10.305 ns ; a[1] ; c[2] ;
; N/A ; None ; 10.303 ns ; a[1] ; c[5] ;
; N/A ; None ; 10.274 ns ; b[1] ; c[6] ;
; N/A ; None ; 10.196 ns ; b[0] ; c[7] ;
; N/A ; None ; 10.189 ns ; a[2] ; c[6] ;
; N/A ; None ; 10.188 ns ; a[3] ; c[4] ;
; N/A ; None ; 10.176 ns ; b[2] ; c[7] ;
; N/A ; None ; 10.170 ns ; b[0] ; c[3] ;
; N/A ; None ; 10.166 ns ; b[0] ; c[1] ;
; N/A ; None ; 10.151 ns ; b[2] ; c[3] ;
; N/A ; None ; 10.146 ns ; b[2] ; c[1] ;
; N/A ; None ; 10.142 ns ; b[2] ; c[2] ;
; N/A ; None ; 10.140 ns ; b[2] ; c[5] ;
; N/A ; None ; 10.136 ns ; b[0] ; c[4] ;
; N/A ; None ; 10.056 ns ; a[0] ; c[6] ;
; N/A ; None ; 9.799 ns ; b[3] ; c[4] ;
; N/A ; None ; 9.673 ns ; a[1] ; c[6] ;
; N/A ; None ; 9.580 ns ; a[3] ; c[7] ;
; N/A ; None ; 9.555 ns ; a[3] ; c[3] ;
; N/A ; None ; 9.550 ns ; a[3] ; c[1] ;
; N/A ; None ; 9.546 ns ; a[3] ; c[2] ;
; N/A ; None ; 9.544 ns ; a[3] ; c[5] ;
; N/A ; None ; 9.510 ns ; b[2] ; c[6] ;
; N/A ; None ; 9.494 ns ; b[0] ; c[2] ;
; N/A ; None ; 9.492 ns ; b[0] ; c[5] ;
; N/A ; None ; 9.191 ns ; b[3] ; c[7] ;
; N/A ; None ; 9.166 ns ; b[3] ; c[3] ;
; N/A ; None ; 9.161 ns ; b[3] ; c[1] ;
; N/A ; None ; 9.157 ns ; b[3] ; c[2] ;
; N/A ; None ; 9.155 ns ; b[3] ; c[5] ;
; N/A ; None ; 8.914 ns ; a[3] ; c[6] ;
; N/A ; None ; 8.862 ns ; b[0] ; c[6] ;
; N/A ; None ; 8.525 ns ; b[3] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jun 24 23:16:59 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[1]" to destination pin "c[7]" is 11.608 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'b[1]'
Info: 2: + IC(2.553 ns) + CELL(0.978 ns) = 4.663 ns; Loc. = LC_X2_Y3_N1; Fanout = 2; COMB Node = 'c_tmp[1]~11'
Info: 3: + IC(0.000 ns) + CELL(0.815 ns) = 5.478 ns; Loc. = LC_X2_Y3_N2; Fanout = 7; COMB Node = 'c_tmp[2]~12'
Info: 4: + IC(1.300 ns) + CELL(0.511 ns) = 7.289 ns; Loc. = LC_X2_Y3_N5; Fanout = 1; COMB Node = 'Mux0~3'
Info: 5: + IC(1.997 ns) + CELL(2.322 ns) = 11.608 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'c[7]'
Info: Total cell delay = 5.758 ns ( 49.60 % )
Info: Total interconnect delay = 5.850 ns ( 50.40 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Jun 24 23:16:59 2008
Info: Elapsed time: 00:00:01
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