led.tan.qmsg

CPLD的小程序集合

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 9 -1 0 } } { "d:/ele_software/quartusii/win/Assignment Editor.qase" "" { Assignment "d:/ele_software/quartusii/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[15\] register cnt\[9\] 66.67 MHz 15.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 66.67 MHz between source register \"cnt\[15\]\" and destination register \"cnt\[9\]\" (period= 15.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest register register " "Info: + Longest register to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[15\] 1 REG LC32 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 28; REG Node = 'cnt\[15\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "" { cnt[15] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns cnt~161 2 COMB LC1 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'cnt~161'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cnt[15] cnt~161 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns cnt~163 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'cnt~163'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "1.000 ns" { cnt~161 cnt~163 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns cnt\[9\] 4 REG LC3 42 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 42; REG Node = 'cnt\[9\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "1.000 ns" { cnt~163 cnt[9] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "10.000 ns" { cnt[15] cnt~161 cnt~163 cnt[9] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "10.000 ns" { cnt[15] cnt~161 cnt~163 cnt[9] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[9\] 2 REG LC3 42 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 42; REG Node = 'cnt\[9\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk cnt[9] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[15\] 2 REG LC32 28 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC32; Fanout = 28; REG Node = 'cnt\[15\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk cnt[15] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[15] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[15] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "10.000 ns" { cnt[15] cnt~161 cnt~163 cnt[9] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "10.000 ns" { cnt[15] cnt~161 cnt~163 cnt[9] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } } { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk cnt[15] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk leddrv\[0\] reg\[0\] 8.000 ns register " "Info: tco from clock \"clk\" to destination pin \"leddrv\[0\]\" through register \"reg\[0\]\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns reg\[0\] 2 REG LC17 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 2; REG Node = 'reg\[0\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk reg[0] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk reg[0] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out reg[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg\[0\] 1 REG LC17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 2; REG Node = 'reg\[0\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "" { reg[0] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns leddrv\[0\] 2 PIN PIN_22 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'leddrv\[0\]'" {  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "4.000 ns" { reg[0] leddrv[0] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/CPLD/LED7/LED.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "4.000 ns" { reg[0] leddrv[0] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "4.000 ns" { reg[0] leddrv[0] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk reg[0] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out reg[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/ele_software/quartusii/win/TimingClosureFloorplan.fld" "" "4.000 ns" { reg[0] leddrv[0] } "NODE_NAME" } } { "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/ele_software/quartusii/win/Technology_Viewer.qrui" "4.000 ns" { reg[0] leddrv[0] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 23:15:11 2008 " "Info: Processing ended: Thu Jan 24 23:15:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}