led.vhd

来自「CPLD的小程序集合」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY  LED IS
  PORT(
    clk     : IN STD_LOGIC;
    leddrv  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END  LED;

ARCHITECTURE maxii_lamp2 OF LED IS
  SIGNAL reg : STD_LOGIC_VECTOR(7 DOWNTO 0) :="00000001";
BEGIN
 
  leddrv <= reg;

  PROCESS(clk)
    VARIABLE cnt : INTEGER RANGE 0 TO 24000000 :=0;
  BEGIN
    IF clk'EVENT AND clk='1' THEN
      cnt := cnt+1;
      IF cnt= 24000000 THEN
        cnt := 0;
        reg <= reg(6 DOWNTO 0)&reg(7);
      END IF;
    END IF;
  END PROCESS;

END maxii_lamp2;