📄 led.tan.rpt
字号:
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[4] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[3] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[2] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[1] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[15] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[14] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[13] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[23] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[22] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[21] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[11] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[10] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[12] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[20] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[19] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[16] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[9] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[8] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[18] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[17] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; cnt[24] ; reg[2] ; clk ; clk ; None ; None ; 8.000 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+---------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+-----------+------------+
; N/A ; None ; 8.000 ns ; reg[0] ; leddrv[0] ; clk ;
; N/A ; None ; 8.000 ns ; reg[7] ; leddrv[7] ; clk ;
; N/A ; None ; 8.000 ns ; reg[6] ; leddrv[6] ; clk ;
; N/A ; None ; 8.000 ns ; reg[5] ; leddrv[5] ; clk ;
; N/A ; None ; 8.000 ns ; reg[4] ; leddrv[4] ; clk ;
; N/A ; None ; 8.000 ns ; reg[3] ; leddrv[3] ; clk ;
; N/A ; None ; 8.000 ns ; reg[2] ; leddrv[2] ; clk ;
; N/A ; None ; 8.000 ns ; reg[1] ; leddrv[1] ; clk ;
+-------+--------------+------------+--------+-----------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Jan 24 23:15:10 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LED -c LED
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 66.67 MHz between source register "cnt[15]" and destination register "cnt[9]" (period= 15.0 ns)
Info: + Longest register to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 28; REG Node = 'cnt[15]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'cnt~161'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'cnt~163'
Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 42; REG Node = 'cnt[9]'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 42; REG Node = 'cnt[9]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock "clk" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC32; Fanout = 28; REG Node = 'cnt[15]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "leddrv[0]" through register "reg[0]" is 8.000 ns
Info: + Longest clock path from clock "clk" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 2; REG Node = 'reg[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 2; REG Node = 'reg[0]'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'leddrv[0]'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Thu Jan 24 23:15:11 2008
Info: Elapsed time: 00:00:01
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