vga.tan.qmsg

CPLD的小程序集合

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cc\[4\] " "Info: Detected ripple clock \"cc\[4\]\" as buffer" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 82 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_int\[1\] " "Info: Detected ripple clock \"clk_int\[1\]\" as buffer" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_int\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fs\[2\] " "Info: Detected ripple clock \"fs\[2\]\" as buffer" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 21 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fs\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ll\[4\] register ll\[5\] 121.49 MHz 8.231 ns Internal " "Info: Clock \"clk\" has Internal fmax of 121.49 MHz between source register \"ll\[4\]\" and destination register \"ll\[5\]\" (period= 8.231 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.522 ns + Longest register register " "Info: + Longest register to register delay is 7.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ll\[4\] 1 REG LC_X3_Y1_N6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y1_N6; Fanout = 8; REG Node = 'll\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ll[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.226 ns) + CELL(0.200 ns) 3.426 ns Equal3~65 2 COMB LC_X4_Y2_N5 5 " "Info: 2: + IC(3.226 ns) + CELL(0.200 ns) = 3.426 ns; Loc. = LC_X4_Y2_N5; Fanout = 5; COMB Node = 'Equal3~65'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.426 ns" { ll[4] Equal3~65 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.292 ns) + CELL(0.804 ns) 7.522 ns ll\[5\] 3 REG LC_X2_Y1_N3 9 " "Info: 3: + IC(3.292 ns) + CELL(0.804 ns) = 7.522 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.096 ns" { Equal3~65 ll[5] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.004 ns ( 13.35 % ) " "Info: Total cell delay = 1.004 ns ( 13.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.518 ns ( 86.65 % ) " "Info: Total interconnect delay = 6.518 ns ( 86.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.522 ns" { ll[4] Equal3~65 ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.522 ns" { ll[4] Equal3~65 ll[5] } { 0.000ns 3.226ns 3.292ns } { 0.000ns 0.200ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.693 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 16.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clk_int\[1\] 2 REG LC_X2_Y4_N3 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk_int[1] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 8.534 ns fs\[2\] 3 REG LC_X3_Y3_N2 6 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.810 ns" { clk_int[1] fs[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 13.029 ns cc\[4\] 4 REG LC_X2_Y3_N4 15 " "Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.495 ns" { fs[2] cc[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 16.693 ns ll\[5\] 5 REG LC_X2_Y1_N3 9 " "Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { cc[4] ll[5] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 35.72 % ) " "Info: Total cell delay = 5.963 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.730 ns ( 64.28 % ) " "Info: Total interconnect delay = 10.730 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[5] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.693 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 16.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clk_int\[1\] 2 REG LC_X2_Y4_N3 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk_int[1] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 8.534 ns fs\[2\] 3 REG LC_X3_Y3_N2 6 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.810 ns" { clk_int[1] fs[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 13.029 ns cc\[4\] 4 REG LC_X2_Y3_N4 15 " "Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.495 ns" { fs[2] cc[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 16.693 ns ll\[4\] 5 REG LC_X3_Y1_N6 8 " "Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X3_Y1_N6; Fanout = 8; REG Node = 'll\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { cc[4] ll[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 35.72 % ) " "Info: Total cell delay = 5.963 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.730 ns ( 64.28 % ) " "Info: Total interconnect delay = 10.730 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[4] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[5] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[4] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.522 ns" { ll[4] Equal3~65 ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.522 ns" { ll[4] Equal3~65 ll[5] } { 0.000ns 3.226ns 3.292ns } { 0.000ns 0.200ns 0.804ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[5] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[4] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "mmd\[0\] orient clk 3.133 ns register " "Info: tsu for register \"mmd\[0\]\" (data pin = \"orient\", clock pin = \"clk\") is 3.133 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.148 ns + Longest pin register " "Info: + Longest pin to register delay is 6.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns orient 1 PIN PIN_27 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 5; PIN Node = 'orient'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { orient } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.773 ns) + CELL(1.243 ns) 6.148 ns mmd\[0\] 2 REG LC_X2_Y2_N9 7 " "Info: 2: + IC(3.773 ns) + CELL(1.243 ns) = 6.148 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.016 ns" { orient mmd[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns ( 38.63 % ) " "Info: Total cell delay = 2.375 ns ( 38.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.773 ns ( 61.37 % ) " "Info: Total interconnect delay = 3.773 ns ( 61.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.148 ns" { orient mmd[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.148 ns" { orient orient~combout mmd[0] } { 0.000ns 0.000ns 3.773ns } { 0.000ns 1.132ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns mmd\[0\] 2 REG LC_X2_Y2_N9 7 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk mmd[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk mmd[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout mmd[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.148 ns" { orient mmd[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.148 ns" { orient orient~combout mmd[0] } { 0.000ns 0.000ns 3.773ns } { 0.000ns 1.132ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk mmd[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout mmd[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk r ll\[5\] 27.526 ns register " "Info: tco from clock \"clk\" to destination pin \"r\" through register \"ll\[5\]\" is 27.526 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.693 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 16.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clk_int\[1\] 2 REG LC_X2_Y4_N3 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk_int[1] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(1.294 ns) 8.534 ns fs\[2\] 3 REG LC_X3_Y3_N2 6 " "Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.810 ns" { clk_int[1] fs[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 13.029 ns cc\[4\] 4 REG LC_X2_Y3_N4 15 " "Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.495 ns" { fs[2] cc[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 16.693 ns ll\[5\] 5 REG LC_X2_Y1_N3 9 " "Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { cc[4] ll[5] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 35.72 % ) " "Info: Total cell delay = 5.963 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.730 ns ( 64.28 % ) " "Info: Total interconnect delay = 10.730 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[5] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.457 ns + Longest register pin " "Info: + Longest register to pin delay is 10.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ll\[5\] 1 REG LC_X2_Y1_N3 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ll[5] } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.914 ns) 2.868 ns LessThan14~84 2 COMB LC_X3_Y1_N6 2 " "Info: 2: + IC(1.954 ns) + CELL(0.914 ns) = 2.868 ns; Loc. = LC_X3_Y1_N6; Fanout = 2; COMB Node = 'LessThan14~84'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.868 ns" { ll[5] LessThan14~84 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.511 ns) 4.583 ns grb~2100 3 COMB LC_X2_Y1_N0 1 " "Info: 3: + IC(1.204 ns) + CELL(0.511 ns) = 4.583 ns; Loc. = LC_X2_Y1_N0; Fanout = 1; COMB Node = 'grb~2100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.715 ns" { LessThan14~84 grb~2100 } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.740 ns) 6.046 ns grb~2104 4 COMB LC_X2_Y1_N8 1 " "Info: 4: + IC(0.723 ns) + CELL(0.740 ns) = 6.046 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'grb~2104'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.463 ns" { grb~2100 grb~2104 } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.089 ns) + CELL(2.322 ns) 10.457 ns r 5 PIN PIN_2 0 " "Info: 5: + IC(2.089 ns) + CELL(2.322 ns) = 10.457 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'r'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.411 ns" { grb~2104 r } "NODE_NAME" } } { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.487 ns ( 42.91 % ) " "Info: Total cell delay = 4.487 ns ( 42.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.970 ns ( 57.09 % ) " "Info: Total interconnect delay = 5.970 ns ( 57.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.457 ns" { ll[5] LessThan14~84 grb~2100 grb~2104 r } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.457 ns" { ll[5] LessThan14~84 grb~2100 grb~2104 r } { 0.000ns 1.954ns 1.204ns 0.723ns 2.089ns } { 0.000ns 0.914ns 0.511ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.693 ns" { clk clk_int[1] fs[2] cc[4] ll[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.693 ns" { clk clk~combout clk_int[1] fs[2] cc[4] ll[5] } { 0.000ns 0.000ns 1.267ns 3.516ns 3.201ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.457 ns" { ll[5] LessThan14~84 grb~2100 grb~2104 r } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.457 ns" { ll[5] LessThan14~84 grb~2100 grb~2104 r } { 0.000ns 1.954ns 1.204ns 0.723ns 2.089ns } { 0.000ns 0.914ns 0.511ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}