vga.map.qmsg

CPLD的小程序集合

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 14 20:36:46 2009 " "Info: Processing started: Sat Feb 14 20:36:46 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga-behv " "Info: Found design unit 1: vga-behv" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA " "Info: Elaborating entity \"VGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk VGA.vhd(43) " "Warning (10492): VHDL Process Statement warning at VGA.vhd(43): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 43 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "grbx VGA.vhd(57) " "Warning (10492): VHDL Process Statement warning at VGA.vhd(57): signal \"grbx\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 57 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "grby VGA.vhd(59) " "Warning (10492): VHDL Process Statement warning at VGA.vhd(59): signal \"grby\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 59 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "grbx VGA.vhd(61) " "Warning (10492): VHDL Process Statement warning at VGA.vhd(61): signal \"grbx\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 61 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "grby VGA.vhd(61) " "Warning (10492): VHDL Process Statement warning at VGA.vhd(61): signal \"grby\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGA.vhd" "" { Text "F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd" 61 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "64 " "Info: Implemented 64 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "57 " "Info: Implemented 57 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 14 20:36:51 2009 " "Info: Processing ended: Sat Feb 14 20:36:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}