vga.tan.rpt

CPLD的小程序集合

Timing Analyzer report for VGA
Sat Feb 14 20:37:01 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. tpd
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                          ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From   ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.133 ns                         ; orient ; mmd[1] ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 27.526 ns                        ; ll[5]  ; r      ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 8.557 ns                         ; orient ; g      ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -2.579 ns                        ; orient ; mmd[1] ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 121.49 MHz ( period = 8.231 ns ) ; ll[4]  ; ll[5]  ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;        ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                           ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From       ; To         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 121.49 MHz ( period = 8.231 ns )               ; ll[4]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 7.522 ns                ;
; N/A   ; 126.14 MHz ( period = 7.928 ns )               ; ll[2]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 7.219 ns                ;
; N/A   ; 128.70 MHz ( period = 7.770 ns )               ; ll[3]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 7.061 ns                ;
; N/A   ; 131.11 MHz ( period = 7.627 ns )               ; ll[6]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 6.918 ns                ;
; N/A   ; 134.28 MHz ( period = 7.447 ns )               ; ll[4]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.738 ns                ;
; N/A   ; 134.30 MHz ( period = 7.446 ns )               ; ll[4]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 6.737 ns                ;
; N/A   ; 135.87 MHz ( period = 7.360 ns )               ; ll[0]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 6.651 ns                ;
; N/A   ; 135.87 MHz ( period = 7.360 ns )               ; ll[5]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.651 ns                ;
; N/A   ; 136.05 MHz ( period = 7.350 ns )               ; ll[5]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 6.641 ns                ;
; N/A   ; 137.85 MHz ( period = 7.254 ns )               ; ll[2]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.545 ns                ;
; N/A   ; 139.33 MHz ( period = 7.177 ns )               ; ll[1]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 6.468 ns                ;
; N/A   ; 139.65 MHz ( period = 7.161 ns )               ; ll[3]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.452 ns                ;
; N/A   ; 140.00 MHz ( period = 7.143 ns )               ; ll[2]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 6.434 ns                ;
; N/A   ; 140.11 MHz ( period = 7.137 ns )               ; ll[7]      ; ll[1]      ; clk        ; clk      ; None                        ; None                      ; 6.428 ns                ;
; N/A   ; 141.38 MHz ( period = 7.073 ns )               ; ll[4]      ; ll[1]      ; clk        ; clk      ; None                        ; None                      ; 6.364 ns                ;
; N/A   ; 141.54 MHz ( period = 7.065 ns )               ; ll[5]      ; ll[5]      ; clk        ; clk      ; None                        ; None                      ; 6.356 ns                ;
; N/A   ; 141.58 MHz ( period = 7.063 ns )               ; ll[2]      ; ll[4]      ; clk        ; clk      ; None                        ; None                      ; 6.354 ns                ;
; N/A   ; 141.64 MHz ( period = 7.060 ns )               ; ll[7]      ; ll[8]      ; clk        ; clk      ; None                        ; None                      ; 6.351 ns                ;
; N/A   ; 142.29 MHz ( period = 7.028 ns )               ; ll[3]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 6.319 ns                ;
; N/A   ; 143.47 MHz ( period = 6.970 ns )               ; ll[3]      ; ll[4]      ; clk        ; clk      ; None                        ; None                      ; 6.261 ns                ;
; N/A   ; 144.13 MHz ( period = 6.938 ns )               ; ll[6]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.229 ns                ;
; N/A   ; 145.90 MHz ( period = 6.854 ns )               ; ll[4]      ; ll[8]      ; clk        ; clk      ; None                        ; None                      ; 6.145 ns                ;
; N/A   ; 146.35 MHz ( period = 6.833 ns )               ; ll[0]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 6.124 ns                ;
; N/A   ; 147.71 MHz ( period = 6.770 ns )               ; ll[2]      ; ll[1]      ; clk        ; clk      ; None                        ; None                      ; 6.061 ns                ;
; N/A   ; 149.25 MHz ( period = 6.700 ns )               ; ll[0]      ; ll[7]      ; clk        ; clk      ; None                        ; None                      ; 5.991 ns                ;
; N/A   ; 150.38 MHz ( period = 6.650 ns )               ; ll[1]      ; ll[6]      ; clk        ; clk      ; None                        ; None                      ; 5.941 ns                ;