vga.fit.rpt

CPLD的小程序集合

+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 12          ;
; Mid Slack - Fit Attempt 1                                                      ; -25057      ;
; Internal Atom Count - Fit Attempt 1                                            ; 54          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 54          ;
; LAB Count - Fit Attempt 1                                                      ; 9           ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.333       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.667       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.000       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:9         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:8;1:1     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:8;1:1     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:8;1:1     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:8;1:1     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:8;1:1     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:9         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:9         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:8;1:1     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:7;2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:7;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:9         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:8     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:8;1:1     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:3;1:6     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:9         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:9         ;
; LEs in Chains - Fit Attempt 1                                                  ; 13          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 2           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016       ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Early Slack - Fit Attempt 1         ; -30677 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 5      ;
; Mid Slack - Fit Attempt 1           ; -27830 ;
; Late Wire Use - Fit Attempt 1       ; 5      ;
; Late Slack - Fit Attempt 1          ; -27830 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.078  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -25387 ;
; Early Wire Use - Fit Attempt 1      ; 4      ;
; Peak Regional Wire - Fit Attempt 1  ; 4      ;
; Mid Slack - Fit Attempt 1           ; -27016 ;
; Late Slack - Fit Attempt 1          ; -27031 ;
; Late Slack - Fit Attempt 1          ; -27031 ;
; Late Wire Use - Fit Attempt 1       ; 8      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.094  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Feb 14 20:36:53 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off VGA -c VGA
Info: Selected device EPM240T100C5 for design "VGA"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "cc[4]" to use Global clock
    Info: Destination "cc[4]" may be non-global or may not use global clock
    Info: Destination "LessThan0~47" may be non-global or may not use global clock
    Info: Destination "grb~2098" may be non-global or may not use global clock
    Info: Destination "grb~2102" may be non-global or may not use global clock
    Info: Destination "grb~2106" may be non-global or may not use global clock
    Info: Destination "grb~2114" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "fs[2]" to use Global clock
    Info: Destination "fs[2]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clk_int[1]" to use Global clock
    Info: Destination "clk_int[1]" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 10.272 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y1; Fanout = 6; REG Node = 'll[2]'
    Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'grb~2108'
    Info: 3: + IC(0.266 ns) + CELL(0.914 ns) = 2.612 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'grb~2109'
    Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 3.792 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'grb~2110'
    Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 4.972 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'grb~2111'
    Info: 6: + IC(0.669 ns) + CELL(0.511 ns) = 6.152 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'grb~2115'
    Info: 7: + IC(1.798 ns) + CELL(2.322 ns) = 10.272 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'b'
    Info: Total cell delay = 5.601 ns ( 54.53 % )
    Info: Total interconnect delay = 4.671 ns ( 45.47 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Feb 14 20:36:56 2009
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/EPM240开发板/EPM240程序/VGA2/VGA.fit.smsg.