vga.map.rpt

来自「CPLD的小程序集合」· RPT 代码 · 共 206 行 · 第 1/2 页

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                         ;
+----------------------------------+-----------------+-----------------+-----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path            ;
+----------------------------------+-----------------+-----------------+-----------------------------------------+
; VGA.vhd                          ; yes             ; User VHDL File  ; F:/EPM240开发板/EPM240程序/VGA2/VGA.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 57    ;
;     -- Combinational with no register       ; 36    ;
;     -- Register only                        ; 4     ;
;     -- Combinational with a register        ; 17    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 24    ;
;     -- 3 input functions                    ; 6     ;
;     -- 2 input functions                    ; 19    ;
;     -- 1 input functions                    ; 4     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 46    ;
;     -- arithmetic mode                      ; 11    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 21    ;
; Total logic cells in carry chains           ; 13    ;
; I/O pins                                    ; 7     ;
; Maximum fan-out node                        ; cc[4] ;
; Maximum fan-out                             ; 15    ;
; Total fan-out                               ; 188   ;
; Average fan-out                             ; 2.94  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |vga                       ; 57 (57)     ; 21           ; 0          ; 7    ; 0            ; 36 (36)      ; 4 (4)             ; 17 (17)          ; 13 (13)         ; 0 (0)      ; |vga                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 21    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Feb 14 20:36:46 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA
Info: Found 2 design units, including 1 entities, in source file VGA.vhd
    Info: Found design unit 1: vga-behv
    Info: Found entity 1: vga
Info: Elaborating entity "VGA" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at VGA.vhd(43): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at VGA.vhd(57): signal "grbx" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at VGA.vhd(59): signal "grby" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at VGA.vhd(61): signal "grbx" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at VGA.vhd(61): signal "grby" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 64 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 57 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Feb 14 20:36:51 2009
    Info: Elapsed time: 00:00:05