vga.vhd

CPLD的小程序集合

--********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--********************************************
ENTITY vga is
PORT (
      clk,orient : IN STD_LOGIC;
      hs,vs,r,g,b: out std_logic
      );
END vga;

--*********************************************
ARCHITECTURE behv OF vga IS
signal clk_int :std_logic_vector(1 downto 0);
signal hs1,vs1,fclk,cclk: STD_LOGIC;
signal mmd: STD_LOGIC_vector(1 downto 0);
signal fs: STD_LOGIC_vector(3 downto 0);
signal cc: STD_LOGIC_vector(4 downto 0);
signal ll: STD_LOGIC_vector(8 downto 0);
signal grbx: STD_LOGIC_vector(3 downto 1);
signal grby: STD_LOGIC_vector(3 downto 1);
signal grbp: STD_LOGIC_vector(3 downto 1);
signal grb: STD_LOGIC_vector(3 downto 1);

BEGIN
PROCESS(CLK)
begin
   if(clk'event and clk='1')then
    clk_int<=clk_int+1;
   end if;
end process;

grb(2)<=(grbp(2) xor orient) and hs1 and vs1;
grb(3)<=(grbp(3) xor orient) and hs1 and vs1;
grb(1)<=(grbp(1) xor orient) and hs1 and vs1;
--**************************************************
process(orient)
begin
  if clk'event and clk='0' then
  if(orient ='0' )then
  if mmd="10" then
    mmd<="00";
  else
    mmd<=mmd+1;
  end if;
  end if;
  end if;
end process;
--****************************************************
process(mmd)
begin
   if( mmd="00") then
    grbp<=grbx;
   elsif (mmd="01") then
    grbp<=grby;
   elsif (mmd="10") then
    grbp<=grbx xor grby;
    else
    grbp<="000";
    end if;
end process;
--************************************************
process(clk_int(1))
begin
if clk_int(1)'event and clk_int(1)='1' then
    if fs=24 then
     fs<="0000";
    else
     fs<=fs+1;
    end if;
    end if;
end process;
--**************************************************
fclk<=fs(2);

process(fclk)
begin
  if fclk'event and fclk='1' then
    if cc=48 then
     cc<="00000";
    else
     cc<=cc+1;
    end if;
  end if;
end process;

cclk<=cc(4);
--***************************************************
process(cclk)
begin
if cclk'event and cclk='0' then
   if ll=481 then
     ll<=(others=>'0');
       else
       ll<=ll+1;
      end if;
   end if;
end process;
--*******************************************************
process(cc,ll)
begin
if cc>23 then
   hs1<='0';
   else
   hs1<='1';
   end if;
   if ll>479 then
   vs1<='0';
   else
   vs1<='1';
 end if;
end process;
--********************************************************
process(cc,ll)
begin
if cc<3 then grbx<="111";
   elsif cc<6 then grbx<="110";
   elsif cc<9 then grbx<="101";
   elsif cc<12 then grbx<="100";
   elsif cc<15 then grbx<="011";
   elsif cc<18 then grbx<="010";
   elsif cc<21 then grbx<="001";
   else grbx<="000";
end if;

if ll<60 then grby<="111";
   elsif ll<120 then grby<="110";
   elsif ll<180 then grby<="101";
   elsif ll<240 then grby<="100";
   elsif ll<300 then grby<="011";
   elsif ll<360 then grby<="010";
   elsif ll<420 then grby<="001";
   else grby<="000";
end if;
end process;
   hs<=hs1;
   vs<=vs1;
   r<=grb(2);
   g<=grb(3);
   b<=grb(1);
end behv;