seg73.tan.qmsg

CPLD的小程序集合

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "first_over " "Info: Detected ripple clock \"first_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 26 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "first_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 37 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "third_over " "Info: Detected ripple clock \"third_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "third_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second_over " "Info: Detected ripple clock \"second_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register last_over register cntfirst\[3\] 67.29 MHz 14.861 ns Internal " "Info: Clock \"clk\" has Internal fmax of 67.29 MHz between source register \"last_over\" and destination register \"cntfirst\[3\]\" (period= 14.861 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.464 ns + Longest register register " "Info: + Longest register to register delay is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns last_over 1 REG LC_X2_Y3_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N9; Fanout = 3; REG Node = 'last_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { last_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.200 ns) 1.127 ns process1~0 2 COMB LC_X2_Y3_N3 3 " "Info: 2: + IC(0.927 ns) + CELL(0.200 ns) = 1.127 ns; Loc. = LC_X2_Y3_N3; Fanout = 3; COMB Node = 'process1~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.127 ns" { last_over process1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.591 ns) 2.464 ns cntfirst\[3\] 3 REG LC_X2_Y3_N5 4 " "Info: 3: + IC(0.746 ns) + CELL(0.591 ns) = 2.464 ns; Loc. = LC_X2_Y3_N5; Fanout = 4; REG Node = 'cntfirst\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.337 ns" { process1~0 cntfirst[3] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.791 ns ( 32.10 % ) " "Info: Total cell delay = 0.791 ns ( 32.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.673 ns ( 67.90 % ) " "Info: Total interconnect delay = 1.673 ns ( 67.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.464 ns" { last_over process1~0 cntfirst[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.464 ns" { last_over process1~0 cntfirst[3] } { 0.000ns 0.927ns 0.746ns } { 0.000ns 0.200ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-11.688 ns - Smallest " "Info: - Smallest clock skew is -11.688 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.639 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 29 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y2_N6 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y2_N6; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.997 ns) + CELL(0.918 ns) 8.639 ns cntfirst\[3\] 3 REG LC_X2_Y3_N5 4 " "Info: 3: + IC(3.997 ns) + CELL(0.918 ns) = 8.639 ns; Loc. = LC_X2_Y3_N5; Fanout = 4; REG Node = 'cntfirst\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.915 ns" { div_cnt[24] cntfirst[3] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.07 % ) " "Info: Total cell delay = 3.375 ns ( 39.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.264 ns ( 60.93 % ) " "Info: Total interconnect delay = 5.264 ns ( 60.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.639 ns" { clk div_cnt[24] cntfirst[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.639 ns" { clk clk~combout div_cnt[24] cntfirst[3] } { 0.000ns 0.000ns 1.267ns 3.997ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.327 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 20.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 29 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y2_N6 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y2_N6; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.997 ns) + CELL(1.294 ns) 9.015 ns first_over 3 REG LC_X2_Y3_N3 5 " "Info: 3: + IC(3.997 ns) + CELL(1.294 ns) = 9.015 ns; Loc. = LC_X2_Y3_N3; Fanout = 5; REG Node = 'first_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.291 ns" { div_cnt[24] first_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(1.294 ns) 13.057 ns second_over 4 REG LC_X3_Y3_N7 5 " "Info: 4: + IC(2.748 ns) + CELL(1.294 ns) = 13.057 ns; Loc. = LC_X3_Y3_N7; Fanout = 5; REG Node = 'second_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.042 ns" { first_over second_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.204 ns) + CELL(1.294 ns) 17.555 ns third_over 5 REG LC_X6_Y3_N3 5 " "Info: 5: + IC(3.204 ns) + CELL(1.294 ns) = 17.555 ns; Loc. = LC_X6_Y3_N3; Fanout = 5; REG Node = 'third_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.498 ns" { second_over third_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.854 ns) + CELL(0.918 ns) 20.327 ns last_over 6 REG LC_X2_Y3_N9 3 " "Info: 6: + IC(1.854 ns) + CELL(0.918 ns) = 20.327 ns; Loc. = LC_X2_Y3_N9; Fanout = 3; REG Node = 'last_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.772 ns" { third_over last_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.257 ns ( 35.70 % ) " "Info: Total cell delay = 7.257 ns ( 35.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.070 ns ( 64.30 % ) " "Info: Total interconnect delay = 13.070 ns ( 64.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.327 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "20.327 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 1.267ns 3.997ns 2.748ns 3.204ns 1.854ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.639 ns" { clk div_cnt[24] cntfirst[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.639 ns" { clk clk~combout div_cnt[24] cntfirst[3] } { 0.000ns 0.000ns 1.267ns 3.997ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.327 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "20.327 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 1.267ns 3.997ns 2.748ns 3.204ns 1.854ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.464 ns" { last_over process1~0 cntfirst[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.464 ns" { last_over process1~0 cntfirst[3] } { 0.000ns 0.927ns 0.746ns } { 0.000ns 0.200ns 0.591ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.639 ns" { clk div_cnt[24] cntfirst[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.639 ns" { clk clk~combout div_cnt[24] cntfirst[3] } { 0.000ns 0.000ns 1.267ns 3.997ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.327 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "20.327 ns" { clk clk~combout div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 1.267ns 3.997ns 2.748ns 3.204ns 1.854ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[0\] cntlast\[3\] 28.174 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[0\]\" through register \"cntlast\[3\]\" is 28.174 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.746 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 19.746 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 29 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y2_N6 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y2_N6; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.997 ns) + CELL(1.294 ns) 9.015 ns first_over 3 REG LC_X2_Y3_N3 5 " "Info: 3: + IC(3.997 ns) + CELL(1.294 ns) = 9.015 ns; Loc. = LC_X2_Y3_N3; Fanout = 5; REG Node = 'first_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.291 ns" { div_cnt[24] first_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(1.294 ns) 13.057 ns second_over 4 REG LC_X3_Y3_N7 5 " "Info: 4: + IC(2.748 ns) + CELL(1.294 ns) = 13.057 ns; Loc. = LC_X3_Y3_N7; Fanout = 5; REG Node = 'second_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.042 ns" { first_over second_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.204 ns) + CELL(1.294 ns) 17.555 ns third_over 5 REG LC_X6_Y3_N3 5 " "Info: 5: + IC(3.204 ns) + CELL(1.294 ns) = 17.555 ns; Loc. = LC_X6_Y3_N3; Fanout = 5; REG Node = 'third_over'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.498 ns" { second_over third_over } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.918 ns) 19.746 ns cntlast\[3\] 6 REG LC_X7_Y3_N9 4 " "Info: 6: + IC(1.273 ns) + CELL(0.918 ns) = 19.746 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'cntlast\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.191 ns" { third_over cntlast[3] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.257 ns ( 36.75 % ) " "Info: Total cell delay = 7.257 ns ( 36.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.489 ns ( 63.25 % ) " "Info: Total interconnect delay = 12.489 ns ( 63.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.746 ns" { clk div_cnt[24] first_over second_over third_over cntlast[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.746 ns" { clk clk~combout div_cnt[24] first_over second_over third_over cntlast[3] } { 0.000ns 0.000ns 1.267ns 3.997ns 2.748ns 3.204ns 1.273ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 96 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.052 ns + Longest register pin " "Info: + Longest register to pin delay is 8.052 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntlast\[3\] 1 REG LC_X7_Y3_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'cntlast\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cntlast[3] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.200 ns) 1.190 ns Mux4~182 2 COMB LC_X7_Y3_N3 1 " "Info: 2: + IC(0.990 ns) + CELL(0.200 ns) = 1.190 ns; Loc. = LC_X7_Y3_N3; Fanout = 1; COMB Node = 'Mux4~182'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.190 ns" { cntlast[3] Mux4~182 } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.200 ns) 2.099 ns Mux4~183 3 COMB LC_X7_Y3_N2 8 " "Info: 3: + IC(0.709 ns) + CELL(0.200 ns) = 2.099 ns; Loc. = LC_X7_Y3_N2; Fanout = 8; COMB Node = 'Mux4~183'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.909 ns" { Mux4~182 Mux4~183 } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.511 ns) 3.813 ns Mux15~17 4 COMB LC_X6_Y3_N2 1 " "Info: 4: + IC(1.203 ns) + CELL(0.511 ns) = 3.813 ns; Loc. = LC_X6_Y3_N2; Fanout = 1; COMB Node = 'Mux15~17'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.714 ns" { Mux4~183 Mux15~17 } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 147 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.917 ns) + CELL(2.322 ns) 8.052 ns dataout\[0\] 5 PIN PIN_85 0 " "Info: 5: + IC(1.917 ns) + CELL(2.322 ns) = 8.052 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'dataout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.239 ns" { Mux15~17 dataout[0] } "NODE_NAME" } } { "seg73.vhd" "" { Text "E:/EPM240程序/0000-9999/seg73/seg73.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.233 ns ( 40.15 % ) " "Info: Total cell delay = 3.233 ns ( 40.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.819 ns ( 59.85 % ) " "Info: Total interconnect delay = 4.819 ns ( 59.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.052 ns" { cntlast[3] Mux4~182 Mux4~183 Mux15~17 dataout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.052 ns" { cntlast[3] Mux4~182 Mux4~183 Mux15~17 dataout[0] } { 0.000ns 0.990ns 0.709ns 1.203ns 1.917ns } { 0.000ns 0.200ns 0.200ns 0.511ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.746 ns" { clk div_cnt[24] first_over second_over third_over cntlast[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.746 ns" { clk clk~combout div_cnt[24] first_over second_over third_over cntlast[3] } { 0.000ns 0.000ns 1.267ns 3.997ns 2.748ns 3.204ns 1.273ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.052 ns" { cntlast[3] Mux4~182 Mux4~183 Mux15~17 dataout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.052 ns" { cntlast[3] Mux4~182 Mux4~183 Mux15~17 dataout[0] } { 0.000ns 0.990ns 0.709ns 1.203ns 1.917ns } { 0.000ns 0.200ns 0.200ns 0.511ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 12 20:04:45 2009 " "Info: Processing ended: Thu Feb 12 20:04:45 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}