来自「CPLD的小程序集合」· 代码 · 共 17 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "RXD " "Info: Assuming node \"RXD\" is an undefined clock" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 19 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "RXD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Count\[2\] " "Info: Detected ripple clock \"Count\[2\]\" as buffer" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "Count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register cnt8\[1\] register spdata\[8\] 141.7 MHz 7.057 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 141.7 MHz between source register \"cnt8\[1\]\" and destination register \"spdata\[8\]\" (period= 7.057 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.348 ns + Longest register register " "Info: + Longest register to register delay is 6.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt8\[1\] 1 REG LC_X4_Y3_N3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N3; Fanout = 14; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt8[1] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.440 ns) + CELL(0.914 ns) 3.354 ns Decoder0~151 2 COMB LC_X7_Y2_N4 1 " "Info: 2: + IC(2.440 ns) + CELL(0.914 ns) = 3.354 ns; Loc. = LC_X7_Y2_N4; Fanout = 1; COMB Node = 'Decoder0~151'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.354 ns" { cnt8[1] Decoder0~151 } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.403 ns) + CELL(0.591 ns) 6.348 ns spdata\[8\] 3 REG LC_X2_Y3_N8 2 " "Info: 3: + IC(2.403 ns) + CELL(0.591 ns) = 6.348 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.994 ns" { Decoder0~151 spdata[8] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 23.71 % ) " "Info: Total cell delay = 1.505 ns ( 23.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.843 ns ( 76.29 % ) " "Info: Total interconnect delay = 4.843 ns ( 76.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.348 ns" { cnt8[1] Decoder0~151 spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.348 ns" { cnt8[1] {} Decoder0~151 {} spdata[8] {} } { 0.000ns 2.440ns 2.403ns } { 0.000ns 0.914ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.488 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 8.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns Count\[2\] 2 REG LC_X3_Y2_N5 14 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK Count[2] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.918 ns) 8.488 ns spdata\[8\] 3 REG LC_X2_Y3_N8 2 " "Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { Count[2] spdata[8] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.76 % ) " "Info: Total cell delay = 3.375 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 60.24 % ) " "Info: Total interconnect delay = 5.113 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[8] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.488 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 8.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns Count\[2\] 2 REG LC_X3_Y2_N5 14 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK Count[2] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.918 ns) 8.488 ns cnt8\[1\] 3 REG LC_X4_Y3_N3 14 " "Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X4_Y3_N3; Fanout = 14; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { Count[2] cnt8[1] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.76 % ) " "Info: Total cell delay = 3.375 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 60.24 % ) " "Info: Total interconnect delay = 5.113 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] cnt8[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} cnt8[1] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[8] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] cnt8[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} cnt8[1] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.348 ns" { cnt8[1] Decoder0~151 spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.348 ns" { cnt8[1] {} Decoder0~151 {} spdata[8] {} } { 0.000ns 2.440ns 2.403ns } { 0.000ns 0.914ns 0.591ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[8] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] cnt8[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} cnt8[1] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "RXD " "Info: No valid register-to-register data paths exist for clock \"RXD\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "spdata\[4\] RXD CLK -2.041 ns register " "Info: tsu for register \"spdata\[4\]\" (data pin = \"RXD\", clock pin = \"CLK\") is -2.041 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.114 ns + Longest pin register " "Info: + Longest pin to register delay is 6.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RXD 1 CLK PIN_4 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.921 ns) + CELL(1.061 ns) 6.114 ns spdata\[4\] 2 REG LC_X7_Y2_N2 2 " "Info: 2: + IC(3.921 ns) + CELL(1.061 ns) = 6.114 ns; Loc. = LC_X7_Y2_N2; Fanout = 2; REG Node = 'spdata\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.982 ns" { RXD spdata[4] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 35.87 % ) " "Info: Total cell delay = 2.193 ns ( 35.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.921 ns ( 64.13 % ) " "Info: Total interconnect delay = 3.921 ns ( 64.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.114 ns" { RXD spdata[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.114 ns" { RXD {} RXD~combout {} spdata[4] {} } { 0.000ns 0.000ns 3.921ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.488 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 8.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns Count\[2\] 2 REG LC_X3_Y2_N5 14 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK Count[2] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.918 ns) 8.488 ns spdata\[4\] 3 REG LC_X7_Y2_N2 2 " "Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X7_Y2_N2; Fanout = 2; REG Node = 'spdata\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { Count[2] spdata[4] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.76 % ) " "Info: Total cell delay = 3.375 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 60.24 % ) " "Info: Total interconnect delay = 5.113 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[4] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.114 ns" { RXD spdata[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.114 ns" { RXD {} RXD~combout {} spdata[4] {} } { 0.000ns 0.000ns 3.921ns } { 0.000ns 1.132ns 1.061ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[4] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK EOC cnt8\[0\] 16.174 ns register " "Info: tco from clock \"CLK\" to destination pin \"EOC\" through register \"cnt8\[0\]\" is 16.174 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.488 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 8.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns Count\[2\] 2 REG LC_X3_Y2_N5 14 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK Count[2] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.918 ns) 8.488 ns cnt8\[0\] 3 REG LC_X7_Y2_N0 14 " "Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X7_Y2_N0; Fanout = 14; REG Node = 'cnt8\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { Count[2] cnt8[0] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.76 % ) " "Info: Total cell delay = 3.375 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 60.24 % ) " "Info: Total interconnect delay = 5.113 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] cnt8[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} cnt8[0] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.310 ns + Longest register pin " "Info: + Longest register to pin delay is 7.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt8\[0\] 1 REG LC_X7_Y2_N0 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y2_N0; Fanout = 14; REG Node = 'cnt8\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt8[0] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.476 ns) + CELL(0.200 ns) 2.676 ns LessThan0~65 2 COMB LC_X4_Y3_N8 1 " "Info: 2: + IC(2.476 ns) + CELL(0.200 ns) = 2.676 ns; Loc. = LC_X4_Y3_N8; Fanout = 1; COMB Node = 'LessThan0~65'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.676 ns" { cnt8[0] LessThan0~65 } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.312 ns) + CELL(2.322 ns) 7.310 ns EOC 3 PIN PIN_2 0 " "Info: 3: + IC(2.312 ns) + CELL(2.322 ns) = 7.310 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'EOC'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.634 ns" { LessThan0~65 EOC } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 34.50 % ) " "Info: Total cell delay = 2.522 ns ( 34.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.788 ns ( 65.50 % ) " "Info: Total interconnect delay = 4.788 ns ( 65.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { cnt8[0] LessThan0~65 EOC } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { cnt8[0] {} LessThan0~65 {} EOC {} } { 0.000ns 2.476ns 2.312ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] cnt8[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} cnt8[0] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { cnt8[0] LessThan0~65 EOC } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { cnt8[0] {} LessThan0~65 {} EOC {} } { 0.000ns 2.476ns 2.312ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}