来自「CPLD的小程序集合」· 代码 · 共 17 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TPD_RESULT" "RXD TXD 4.922 ns Longest " "Info: Longest tpd from source pin \"RXD\" to destination pin \"TXD\" is 4.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RXD 1 CLK PIN_4 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.468 ns) + CELL(2.322 ns) 4.922 ns TXD 2 PIN PIN_5 0 " "Info: 2: + IC(1.468 ns) + CELL(2.322 ns) = 4.922 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'TXD'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.790 ns" { RXD TXD } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 70.17 % ) " "Info: Total cell delay = 3.454 ns ( 70.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.468 ns ( 29.83 % ) " "Info: Total interconnect delay = 1.468 ns ( 29.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.922 ns" { RXD TXD } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.922 ns" { RXD {} RXD~combout {} TXD {} } { 0.000ns 0.000ns 1.468ns } { 0.000ns 1.132ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "spdata\[8\] RXD CLK 4.519 ns register " "Info: th for register \"spdata\[8\]\" (data pin = \"RXD\", clock pin = \"CLK\") is 4.519 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.488 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 8.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns Count\[2\] 2 REG LC_X3_Y2_N5 14 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK Count[2] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.918 ns) 8.488 ns spdata\[8\] 3 REG LC_X2_Y3_N8 2 " "Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { Count[2] spdata[8] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.76 % ) " "Info: Total cell delay = 3.375 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 60.24 % ) " "Info: Total interconnect delay = 5.113 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[8] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.190 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RXD 1 CLK PIN_4 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.804 ns) 4.190 ns spdata\[8\] 2 REG LC_X2_Y3_N8 2 " "Info: 2: + IC(2.254 ns) + CELL(0.804 ns) = 4.190 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.058 ns" { RXD spdata[8] } "NODE_NAME" } } { "uart.vhd" "" { Text "D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 46.21 % ) " "Info: Total cell delay = 1.936 ns ( 46.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.254 ns ( 53.79 % ) " "Info: Total interconnect delay = 2.254 ns ( 53.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.190 ns" { RXD spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.190 ns" { RXD {} RXD~combout {} spdata[8] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.488 ns" { CLK Count[2] spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.488 ns" { CLK {} CLK~combout {} Count[2] {} spdata[8] {} } { 0.000ns 0.000ns 1.267ns 3.846ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.190 ns" { RXD spdata[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.190 ns" { RXD {} RXD~combout {} spdata[8] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 23:57:08 2009 " "Info: Processing ended: Fri Mar 13 23:57:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}