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; Block Design Naming                                            ; Auto               ; Auto               ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                    ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; uart.vhd                         ; yes             ; User VHDL File  ; D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 29      ;
;     -- Combinational with no register       ; 13      ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 16      ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 12      ;
;     -- 3 input functions                    ; 10      ;
;     -- 2 input functions                    ; 4       ;
;     -- 1 input functions                    ; 2       ;
;     -- 0 input functions                    ; 1       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 29      ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 16      ;
;                                             ;         ;
; Total registers                             ; 16      ;
; I/O pins                                    ; 13      ;
; Maximum fan-out node                        ; cnt8[0] ;
; Maximum fan-out                             ; 14      ;
; Total fan-out                               ; 132     ;
; Average fan-out                             ; 3.14    ;
+---------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |UART                      ; 29 (29)     ; 16           ; 0          ; 13   ; 0            ; 13 (13)      ; 0 (0)             ; 16 (16)          ; 0 (0)           ; 0 (0)      ; |UART               ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; Count[3]                              ; Lost fanout        ;
; Total Number of Removed Registers = 1 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 16    ;
; Number of registers using Asynchronous Load  ; 1     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Fri Mar 13 23:56:57 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
Info: Found 2 design units, including 1 entities, in source file uart.vhd
    Info: Found design unit 1: UART-Behavioral
    Info: Found entity 1: UART
Info: Elaborating entity "uart" for the top level hierarchy
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "Count[3]" lost all its fanouts during netlist optimizations.
Info: Implemented 42 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 10 output pins
    Info: Implemented 29 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 182 megabytes
    Info: Processing ended: Fri Mar 13 23:57:00 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03