来自「CPLD的小程序集合」· 代码 · 共 736 行 · 第 1/5 页

; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 0           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
+--------------------------------------------------------------------------------+-------------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+------------------------------------+--------+
; Name                               ; Value  ;
+------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Mid Wire Use - Fit Attempt 1       ; 3      ;
; Mid Slack - Fit Attempt 1          ; -16900 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Mid Wire Use - Fit Attempt 1       ; 3      ;
; Mid Slack - Fit Attempt 1          ; -16900 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Late Wire Use - Fit Attempt 1      ; 4      ;
; Late Slack - Fit Attempt 1         ; -16900 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000  ;
; Auto Fit Point 7 - Fit Attempt 1   ; ff     ;
; Time - Fit Attempt 1               ; 0      ;
+------------------------------------+--------+


+---------------------------------------------------+
; Advanced Data - Routing                           ;
+-------------------------------------+-------------+
; Name                                ; Value       ;
+-------------------------------------+-------------+
; Early Slack - Fit Attempt 1         ; -15720      ;
; Early Wire Use - Fit Attempt 1      ; 4           ;
; Peak Regional Wire - Fit Attempt 1  ; 3           ;
; Mid Slack - Fit Attempt 1           ; -15742      ;
; Late Slack - Fit Attempt 1          ; -2147483648 ;
; Late Wire Use - Fit Attempt 1       ; 4           ;
; Time - Fit Attempt 1                ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031       ;
+-------------------------------------+-------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Fri Mar 13 23:57:01 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EPM240T100C5 for design "uart"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM240T100A5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
    Info: Device EPM570T100A5 is compatible
Warning: No exact pin location assignment(s) for 13 pins of 13 total pins
    Info: Pin EOC not assigned to an exact location on the device
    Info: Pin PDATA[0] not assigned to an exact location on the device
    Info: Pin PDATA[1] not assigned to an exact location on the device
    Info: Pin PDATA[2] not assigned to an exact location on the device
    Info: Pin PDATA[3] not assigned to an exact location on the device
    Info: Pin PDATA[4] not assigned to an exact location on the device
    Info: Pin PDATA[5] not assigned to an exact location on the device
    Info: Pin PDATA[6] not assigned to an exact location on the device
    Info: Pin PDATA[7] not assigned to an exact location on the device
    Info: Pin TXD not assigned to an exact location on the device
    Info: Pin RXD not assigned to an exact location on the device
    Info: Pin RESET not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "Count[2]" to use Global clock
    Info: Destination "Count[2]" may be non-global or may not use global clock
    Info: Destination "Start~37" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "RESET" to use Global clock in PIN 12
    Info: Destination "Count[3]~0" may be non-global or may not use global clock
Info: Automatically promoted signal "Count[3]~0" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 1 input, 10 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 7.599 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y2; Fanout = 14; REG Node = 'cnt8[0]'
    Info: 2: + IC(2.294 ns) + CELL(0.740 ns) = 3.034 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'LessThan0~65'
    Info: 3: + IC(2.243 ns) + CELL(2.322 ns) = 7.599 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'EOC'
    Info: Total cell delay = 3.062 ns ( 40.29 % )
    Info: Total interconnect delay = 4.537 ns ( 59.71 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources
    Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.fit.smsg
Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed
    Info: Less than 1% of process time was spent using more than one processor
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 187 megabytes
    Info: Processing ended: Fri Mar 13 23:57:03 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/CPLD资料/开发板光盘/EPM240程序/串口/uart.fit.smsg.