来自「CPLD的小程序集合」· 代码 · 共 312 行 · 第 1/3 页

; N/A           ; None        ; 4.519 ns  ; RXD  ; spdata[8] ; CLK      ;
; N/A           ; None        ; 3.953 ns  ; RXD  ; spdata[1] ; CLK      ;
; N/A           ; None        ; 3.941 ns  ; RXD  ; spdata[3] ; CLK      ;
; N/A           ; None        ; 3.940 ns  ; RXD  ; spdata[2] ; CLK      ;
; N/A           ; None        ; 2.602 ns  ; RXD  ; spdata[7] ; CLK      ;
; N/A           ; None        ; 2.601 ns  ; RXD  ; spdata[5] ; CLK      ;
; N/A           ; None        ; 2.596 ns  ; RXD  ; spdata[6] ; CLK      ;
; N/A           ; None        ; 2.595 ns  ; RXD  ; spdata[4] ; CLK      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Fri Mar 13 23:57:07 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "RXD" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "Count[2]" as buffer
Info: Clock "CLK" has Internal fmax of 141.7 MHz between source register "cnt8[1]" and destination register "spdata[8]" (period= 7.057 ns)
    Info: + Longest register to register delay is 6.348 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N3; Fanout = 14; REG Node = 'cnt8[1]'
        Info: 2: + IC(2.440 ns) + CELL(0.914 ns) = 3.354 ns; Loc. = LC_X7_Y2_N4; Fanout = 1; COMB Node = 'Decoder0~151'
        Info: 3: + IC(2.403 ns) + CELL(0.591 ns) = 6.348 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata[8]'
        Info: Total cell delay = 1.505 ns ( 23.71 % )
        Info: Total interconnect delay = 4.843 ns ( 76.29 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 8.488 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count[2]'
            Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata[8]'
            Info: Total cell delay = 3.375 ns ( 39.76 % )
            Info: Total interconnect delay = 5.113 ns ( 60.24 % )
        Info: - Longest clock path from clock "CLK" to source register is 8.488 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count[2]'
            Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X4_Y3_N3; Fanout = 14; REG Node = 'cnt8[1]'
            Info: Total cell delay = 3.375 ns ( 39.76 % )
            Info: Total interconnect delay = 5.113 ns ( 60.24 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: No valid register-to-register data paths exist for clock "RXD"
Info: tsu for register "spdata[4]" (data pin = "RXD", clock pin = "CLK") is -2.041 ns
    Info: + Longest pin to register delay is 6.114 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'
        Info: 2: + IC(3.921 ns) + CELL(1.061 ns) = 6.114 ns; Loc. = LC_X7_Y2_N2; Fanout = 2; REG Node = 'spdata[4]'
        Info: Total cell delay = 2.193 ns ( 35.87 % )
        Info: Total interconnect delay = 3.921 ns ( 64.13 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 8.488 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count[2]'
        Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X7_Y2_N2; Fanout = 2; REG Node = 'spdata[4]'
        Info: Total cell delay = 3.375 ns ( 39.76 % )
        Info: Total interconnect delay = 5.113 ns ( 60.24 % )
Info: tco from clock "CLK" to destination pin "EOC" through register "cnt8[0]" is 16.174 ns
    Info: + Longest clock path from clock "CLK" to source register is 8.488 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count[2]'
        Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X7_Y2_N0; Fanout = 14; REG Node = 'cnt8[0]'
        Info: Total cell delay = 3.375 ns ( 39.76 % )
        Info: Total interconnect delay = 5.113 ns ( 60.24 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 7.310 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y2_N0; Fanout = 14; REG Node = 'cnt8[0]'
        Info: 2: + IC(2.476 ns) + CELL(0.200 ns) = 2.676 ns; Loc. = LC_X4_Y3_N8; Fanout = 1; COMB Node = 'LessThan0~65'
        Info: 3: + IC(2.312 ns) + CELL(2.322 ns) = 7.310 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'EOC'
        Info: Total cell delay = 2.522 ns ( 34.50 % )
        Info: Total interconnect delay = 4.788 ns ( 65.50 % )
Info: Longest tpd from source pin "RXD" to destination pin "TXD" is 4.922 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'
    Info: 2: + IC(1.468 ns) + CELL(2.322 ns) = 4.922 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'TXD'
    Info: Total cell delay = 3.454 ns ( 70.17 % )
    Info: Total interconnect delay = 1.468 ns ( 29.83 % )
Info: th for register "spdata[8]" (data pin = "RXD", clock pin = "CLK") is 4.519 ns
    Info: + Longest clock path from clock "CLK" to destination register is 8.488 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'Count[2]'
        Info: 3: + IC(3.846 ns) + CELL(0.918 ns) = 8.488 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata[8]'
        Info: Total cell delay = 3.375 ns ( 39.76 % )
        Info: Total interconnect delay = 5.113 ns ( 60.24 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 4.190 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 10; CLK Node = 'RXD'
        Info: 2: + IC(2.254 ns) + CELL(0.804 ns) = 4.190 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; REG Node = 'spdata[8]'
        Info: Total cell delay = 1.936 ns ( 46.21 % )
        Info: Total interconnect delay = 2.254 ns ( 53.79 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 126 megabytes
    Info: Processing ended: Fri Mar 13 23:57:08 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01